After Daniel split out this code, I think this makes more sense, and
looks nicer. Also added some comments to help the situation.

Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_reg.h         |   12 ++++++------
 drivers/gpu/drm/i915/intel_ringbuffer.c |   18 +++++++++---------
 drivers/gpu/drm/i915/intel_ringbuffer.h |    4 ++--
 3 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb76b19..645d012 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -241,12 +241,12 @@
 #define  MI_SEMAPHORE_UPDATE       (1<<21)
 #define  MI_SEMAPHORE_COMPARE      (1<<20)
 #define  MI_SEMAPHORE_REGISTER     (1<<18)
-#define  MI_SEMAPHORE_SYNC_RV      (2<<16)
-#define  MI_SEMAPHORE_SYNC_RB      (0<<16)
-#define  MI_SEMAPHORE_SYNC_VR      (0<<16)
-#define  MI_SEMAPHORE_SYNC_VB      (2<<16)
-#define  MI_SEMAPHORE_SYNC_BR      (2<<16)
-#define  MI_SEMAPHORE_SYNC_BV      (0<<16)
+#define  MI_SEMAPHORE_SYNC_RB      (0<<16) /* RCS wait for BCS  (BRSYNC) */
+#define  MI_SEMAPHORE_SYNC_RV      (2<<16) /* RCS wait for VCS  (VRSYNC) */
+#define  MI_SEMAPHORE_SYNC_VR      (0<<16) /* VCS wait for RCS  (RVSYNC) */
+#define  MI_SEMAPHORE_SYNC_VB      (2<<16) /* VCS wait for BCS  (BVSYNC) */
+#define  MI_SEMAPHORE_SYNC_BV      (0<<16) /* BCS wait for VCS  (VBSYNC) */
+#define  MI_SEMAPHORE_SYNC_BR      (2<<16) /* BCS wait for RCS  (RBSYNC) */
 #define  MI_SEMAPHORE_SYNC_INVALID  (1<<0)
 /*
  * 3D instructions used by the kernel
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4161a2d..5b30815 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1330,9 +1330,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
                ring->irq_enable_mask = GT_USER_INTERRUPT;
                ring->get_seqno = gen6_ring_get_seqno;
                ring->sync_to = gen6_ring_sync;
-               ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
-               ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
-               ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
+               ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
+               ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
+               ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
                ring->signal_mbox[0] = GEN6_VRSYNC;
                ring->signal_mbox[1] = GEN6_BRSYNC;
        } else if (IS_GEN5(dev)) {
@@ -1465,9 +1465,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
                ring->irq_put = gen6_ring_put_irq;
                ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
                ring->sync_to = gen6_ring_sync;
-               ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
-               ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
-               ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
+               ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
+               ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
+               ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
                ring->signal_mbox[0] = GEN6_RVSYNC;
                ring->signal_mbox[1] = GEN6_BVSYNC;
        } else {
@@ -1510,9 +1510,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
        ring->irq_put = gen6_ring_put_irq;
        ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
        ring->sync_to = gen6_ring_sync;
-       ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
-       ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
-       ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
+       ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
+       ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
+       ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
        ring->signal_mbox[0] = GEN6_RBSYNC;
        ring->signal_mbox[1] = GEN6_VBSYNC;
        ring->init = init_ring_common;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 55d3da2..0bf7160 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -80,8 +80,8 @@ struct  intel_ring_buffer {
                                   struct intel_ring_buffer *to,
                                   u32 seqno);
 
-       u32             semaphore_register[3]; /*our mbox written by others */
-       u32             signal_mbox[2]; /* mboxes this ring signals to */
+       u32             semaphore_register[I915_NUM_RINGS]; /*our mbox written 
by others */
+       u32             signal_mbox[I915_NUM_RINGS - 1]; /* mboxes this ring 
signals to */
        /**
         * List of objects currently involved in rendering from the
         * ringbuffer.
-- 
1.7.10.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to