From: Ville Syrjälä <ville.syrj...@linux.intel.com>
The hack to grab the pipe A power domain around VLV/CHV cdclk
programming has surely outlived its usefulness. We should be
hold sufficient power domains during any modeset, so let's just
nuke this hack.
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/intel_cdclk.c | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 4fe844c2cc24..0a9175eb7718 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1423,24 +1423,10 @@ static void vlv_modeset_commit_cdclk(struct
drm_atomic_state *old_state)
struct intel_atomic_state *old_intel_state =
to_intel_atomic_state(old_state);
- /*
- * FIXME: We can end up here with all power domains off, yet
- * with a CDCLK frequency other than the minimum. To account
- * for this take the PIPE-A power domain, which covers the HW
- * blocks needed for the following programming. This can be
- * removed once it's guaranteed that we get here either with
- * the minimum CDCLK set, or the required power domains
- * enabled.
- */
- intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
-
if (IS_CHERRYVIEW(dev_priv))
chv_set_cdclk(dev_priv, &old_intel_state->cdclk.actual);
else
vlv_set_cdclk(dev_priv, &old_intel_state->cdclk.actual);
-
-
- intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
}
static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
--
2.10.2
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