On Tue, Dec 13, 2016 at 01:10:59PM +0200, Jani Nikula wrote:
> c9c4b6f6c283 ("drm/i915: fix swizzle detection for gen3") added a
> complicated check for I915G/I945G. Pineview and other gen3 devices match
> IS_MOBILE() anyway. Simplify.
>
> Cc: Daniel Vetter <dan...@ffwll.ch>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index 09193cfb5d8b..e03983973252 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -513,8 +513,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private
> *dev_priv)
> swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> } else if (IS_MOBILE(dev_priv) ||
> - (IS_GEN3(dev_priv) &&
> - !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv))) {
> + IS_I915G(dev_priv) || IS_I945G(dev_priv)) {
Seems to miss i915gm and i945gm. Hm, but then you mention those are
mobile. Then I guess it's a bikeshed, but at least a correct one.
Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch>
-Daniel
> uint32_t dcc;
>
> /* On 9xx chipsets, channel interleave by the CPU is
> --
> 2.1.4
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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