[Intel-gfx] [PATCH 16/25] drm/i915: define Haswell watermarks and clock gating

[Eugeni Dodonov]

For now, we simple reuse the Ivy Bridge routines here.

Signed-off-by: Eugeni Dodonov <eugeni.dodo...@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bd9549d..452a9bc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3685,6 +3685,17 @@ void intel_init_pm(struct drm_device *dev)
                        }
                        dev_priv->display.init_clock_gating = 
ivybridge_init_clock_gating;
                        dev_priv->display.sanitize_pm = gen6_sanitize_pm;
+               } else if (IS_HASWELL(dev)) {
+                       if (SNB_READ_WM0_LATENCY()) {
+                               dev_priv->display.update_wm = 
sandybridge_update_wm;
+                               dev_priv->display.update_sprite_wm = 
sandybridge_update_sprite_wm;
+                       } else {
+                               DRM_DEBUG_KMS("Failed to read display plane 
latency. "
+                                             "Disable CxSR\n");
+                               dev_priv->display.update_wm = NULL;
+                       }
+                       dev_priv->display.init_clock_gating = 
ivybridge_init_clock_gating;
+                       dev_priv->display.sanitize_pm = gen6_sanitize_pm;
                } else
                        dev_priv->display.update_wm = NULL;
        } else if (IS_VALLEYVIEW(dev)) {
-- 
1.7.10

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