Hi Ville,
Thanks for your useful info.
How about L3 cache? In my scenario, Beignet will use Read Write Data
Port to write data (typed write) to bo.
So the cache path is L3 -> LLC -> memory. So only leave LLC cache ability the
same as PTEs is not enough.
In order to make data access efficient, I set L3 to WB. So is there a
way to flush L3 cache to memory?
Thanks,
Chuanbo Weng
-----Original Message-----
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Friday, November 25, 2016 3:07 AM
To: Weng, Chuanbo <chuanbo.w...@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] Does display engine read contents from LLC of scanout
buffer?
On Thu, Nov 24, 2016 at 06:20:22PM +0000, Weng, Chuanbo wrote:
> Hi all,
> I have a question of display (forgive me if it's too simple
> because I'm not familiar with display):
>
> My scenario is as below:
> gbm_bo_create to create gbm_bo
> Get its handle
> drmModeAddFB to specify this bo as scanout
> buffer
> do rendering to this bo by OpenCL(Beignet)
> drmModePageFlip to do page flip
>
> Does display engine directly read contents from scanout
> buffer or read contents from LLC of this scanout buffer?
The display engine sits between the LLC and main memory effectively, so the
answer is that it always reads directly from memory. When you make a bo a
scanout buffer the kernel will flush the caches and reconfigure the PTEs to
UC/WC so that subsequent rendering will hit memory directly.
And that also means you should never override potential scanout buffers to WB
via MOCS, and instead you should leave the choice up to the PTEs.
--
Ville Syrjälä
Intel OTC
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