[Intel-gfx] [PATCH 5/9] drm/i915/glk: Update Port PLL enable sequence for Geminilkae

[Ander Conselvan de Oliveira]

From: Madhav Chauhan <madhav.chau...@intel.com>

Add steps for enabling and disabling Port PLL as per bspec.

Signed-off-by: Madhav Chauhan <madhav.chau...@intel.com>
Signed-off-by: Ander Conselvan de Oliveira 
<ander.conselvan.de.olive...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h       |  2 ++
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 20 ++++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6cff01d..90685d2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1574,6 +1574,8 @@ enum skl_disp_power_wells {
 #define   PORT_PLL_ENABLE              (1 << 31)
 #define   PORT_PLL_LOCK                        (1 << 30)
 #define   PORT_PLL_REF_SEL             (1 << 27)
+#define   PORT_PLL_POWER_ENABLE                (1 << 26)
+#define   PORT_PLL_POWER_STATE         (1 << 25)
 #define BXT_PORT_PLL_ENABLE(port)      _MMIO_PORT(port, _PORT_PLL_A, 
_PORT_PLL_B)
 
 #define _PORT_PLL_EBB_0_A              0x162034
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 63104b7..97f7cc9 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1380,6 +1380,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private 
*dev_priv,
        temp |= PORT_PLL_REF_SEL;
        I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
 
+       if (IS_GEMINILAKE(dev_priv)) {
+               temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
+               temp |= PORT_PLL_POWER_ENABLE;
+               I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
+
+               if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
+                                PORT_PLL_POWER_STATE), 200))
+                       DRM_ERROR("Power state not set for PLL:%d\n", port);
+       }
+
        /* Disable 10 bit clock */
        temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
        temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
@@ -1485,6 +1495,16 @@ static void bxt_ddi_pll_disable(struct drm_i915_private 
*dev_priv,
        temp &= ~PORT_PLL_ENABLE;
        I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
        POSTING_READ(BXT_PORT_PLL_ENABLE(port));
+
+       if (IS_GEMINILAKE(dev_priv)) {
+               temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
+               temp &= ~PORT_PLL_POWER_ENABLE;
+               I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
+
+               if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
+                               PORT_PLL_POWER_STATE), 200))
+                       DRM_ERROR("Power state not reset for PLL:%d\n", port);
+       }
 }
 
 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
-- 
2.5.5

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