If we try to do that and the scanlines just wouldn't advance, we
busy-hang the machine holding the modeset mutex. Not great for
debugging.

References: https://bugzilla.kernel.org/show_bug.cgi?id=43020
Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_crt.c |   21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 0976137..d30779e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -383,6 +383,7 @@ intel_crt_load_detect(struct intel_crt *crt)
        } else {
                bool restore_vblank = false;
                int count, detect;
+               unsigned long timeout;
 
                /*
                * If there isn't any border, add some.
@@ -407,22 +408,32 @@ intel_crt_load_detect(struct intel_crt *crt)
                /*
                 * Wait for the border to be displayed
                 */
-               while (I915_READ(pipe_dsl_reg) >= vactive)
-                       ;
-               while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
-                       ;
+               if (wait_for(I915_READ(pipe_dsl_reg) >= vactive, 1000))
+                       DRM_ERROR("timed out waiting for vactive in "
+                                 "load_detect, scanline: %u\n",
+                                 I915_READ(pipe_dsl_reg));
+               if (wait_for((dsl = I915_READ(pipe_dsl_reg)) <= vsample, 1000))
+                       DRM_ERROR("timed out waiting for vsample in "
+                                 "load_detect, scanline: %u\n",
+                                 I915_READ(pipe_dsl_reg));
                /*
                 * Watch ST00 for an entire scanline
                 */
                detect = 0;
                count = 0;
+               timeout = jiffies + msecs_to_jiffies(1000);
                do {
                        count++;
                        /* Read the ST00 VGA status register */
                        st00 = I915_READ8(VGA_MSR_WRITE);
                        if (st00 & (1 << 4))
                                detect++;
-               } while ((I915_READ(pipe_dsl_reg) == dsl));
+               } while ((I915_READ(pipe_dsl_reg) == dsl) &&
+                        !time_after(jiffies, timeout));
+
+               if (time_after(jiffies, timeout))
+                       DRM_ERROR("timed out while load-detecting, scanline: 
%u\n",
+                                 I915_READ(pipe_dsl_reg));
 
                /* restore vblank if necessary */
                if (restore_vblank)
-- 
1.7.10

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