The docs are not very clear on exactly what this means. Another doc
however mentioned that [not] enabling this can significantly increase
consumption impact.
Some early tests show no perf regression in Nexuiz, but a fairly
significant regression in OA (252FPS -> 240FPS).
Unfortunately I do not have a good setup to check if it actually helps
with power.
v2: move to init_clock_gating function (Ben)
CC: Daniel Vetter <daniel.vet...@ffwll.ch>
Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 972321f..db0b480 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3991,6 +3991,9 @@
#define GEN6_RC6 3
#define GEN6_RC7 4
+#define GEN7_MISCCPCTL 0x9424
+#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
+
#define G4X_AUD_VID_DID 0x62020
#define INTEL_AUDIO_DEVCL 0x808629FB
#define INTEL_AUDIO_DEVBLC 0x80862801
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 33aaad3..f9cbb8d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8938,6 +8938,10 @@ static void ivybridge_init_clock_gating(struct
drm_device *dev)
DISPPLANE_TRICKLE_FEED_DISABLE);
intel_flush_display_plane(dev_priv, pipe);
}
+
+ if (i915_powersave)
+ I915_WRITE(GEN7_MISCCPCTL,
+ I915_READ(GEN7_MISCCPCTL) | GEN7_DOP_CLOCK_GATE_ENABLE);
}
static void valleyview_init_clock_gating(struct drm_device *dev)
--
1.7.10
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