On 02/03/2012 12:22 PM, Eugeni Dodonov wrote:
This adds two cache-related workarounds for Ivy Bridge which can lead to 3D
ring hangs and corruptions.
Signed-off-by: Eugeni Dodonov<eugeni.dodo...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
drivers/gpu/drm/i915/intel_display.c | 6 ++++++
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80fd6b5..92274b1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3028,6 +3028,13 @@
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
#define DISP_FBC_WM_DIS (1<<15)
+/* GEN7 chicken */
+#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
+#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
I'm skeptical of this value. Your mask doesn't match the bits you're
setting:
Actual chicken bits - bitdecode(0x3C4FFF8C & 0x0000ffff):
[2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 15]
Mask bits - bitdecode(0x3C4FFF8C >> 16):
[0, 1, 2, 3, 6, 10, 11, 12, 13]
Also, this is an awful lot of workarounds! I doubt we need all of them.
On the BSpec Workaround page, I see a recommendation to set bits 10
and 26, but I don't see a rationale for the other ones. Is that sufficient?
I'd also prefer to see these broken down into separate #defines for each
bit rather than setting a magical value.
+#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
+#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
+
This WA looks good and matches the docs (vol1i L3 URB > L3 Register
Space (Bspec) > config space for L3 > L3CHMD - l3chicken mode).
/* PCH */
/* south display engine interrupt */
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a72100f..49e5870 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8445,6 +8445,12 @@ static void gen6_init_clock_gating(struct drm_device
*dev)
ILK_DPARB_CLK_GATE |
ILK_DPFD_CLK_GATE);
+ /* IVB workarounds */
+ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
+ GEN7_WA_FOR_GEN7_L3_CONTROL);
+ I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
+ GEN7_WA_L3_CHICKEN_MODE);
+
for_each_pipe(pipe) {
I915_WRITE(DSPCNTR(pipe),
I915_READ(DSPCNTR(pipe)) |
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