We've seen a few patches now which switch the flush enable bit from bit
11 to bit 12 (as the documentation suggests it should be). However this
turned out to be problematic for us.
The simulator has shed some light for us. It's not bit 11, and it's not
bit 12; it's both. Instead of renaming the bits according to the docs
since we're still really not sure, I've decided to just make the
MI_FLUSH_ENABLE be both bits. As an aside, the simulator still makes a
distinction for these two bits, however the error message doesn't seem
to.
I don't believe this is actually required for the simulator to be
function, but it does produce an annoying error message every time
MI_FLUSH is used without this.
Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 771a058..a161ad8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -391,7 +391,7 @@
#define MI_MODE 0x0209c
# define VS_TIMER_DISPATCH (1 << 6)
-# define MI_FLUSH_ENABLE (1 << 11)
+# define MI_FLUSH_ENABLE (3 << 11)
#define GFX_MODE 0x02520
#define GFX_MODE_GEN7 0x0229c
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ca70e2f..e0837fd 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -399,8 +399,9 @@ static int init_render_ring(struct intel_ring_buffer *ring)
if (INTEL_INFO(dev)->gen > 3) {
int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
- if (IS_GEN6(dev) || IS_GEN7(dev))
+ if (IS_GEN6(dev) || IS_GEN7(dev)) {
mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
+ }
I915_WRITE(MI_MODE, mode);
if (IS_GEN7(dev))
I915_WRITE(GFX_MODE_GEN7,
--
1.7.8.3
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