On Thu, 12 Jan 2012 17:29:38 -0200 Eugeni Dodonov <eug...@dodonov.net> wrote:
> On Thu, Jan 12, 2012 at 17:25, Jesse Barnes <jbar...@virtuousgeek.org>wrote: > > > On Thu, 12 Jan 2012 20:08:59 +0100 > > Vincent Vanackere <vincent.vanack...@gmail.com> wrote: > > > > Thanks for the report... do you also have: > > > > > > > > commit 7a4198664d46b87025a64530f1530ab2bea54c19 > > > > Author: Jesse Barnes <jbar...@virtuousgeek.org> > > > > Date: Tue Nov 15 10:28:53 2011 -0800 > > > > > > > > drm/i915: don't disable a PCH DPLL that's in use > > > > > > > > > > > > commit d8e70a254d8f2da141006e496a51502b79115e80 > > > > Author: Jesse Barnes <jbar...@virtuousgeek.org> > > > > Date: Tue Nov 15 10:28:54 2011 -0800 > > > > > > > > drm/i915: only set the intel_crtc DPMS mode to on if the mode set > > > > succeeded > > > > > > > > in your tree? Those are needed to fix some 3 pipe related bugs. > > > > > > > > -- > > > > Jesse Barnes, Intel Open Source Technology Center > > > > > > > > > > Yes, these commits were present. To double-check I just tested the latest > > > tip at a429638cac1e5c656818a45aaff78df7b743004e and the problem is still > > > there. > > > > Stefan, you have the same machine? I wonder if it's an eDP config; my > > t420 here works ok with current bits, but it uses LVDS. > > > > If you are using eDP, you might be facing > https://bugs.freedesktop.org/show_bug.cgi?id=42263 or > https://bugs.freedesktop.org/show_bug.cgi?id=42278. > > Could you try with patch mentioned at > https://bugs.freedesktop.org/show_bug.cgi?id=42263 reverted? Also can you try this patch as a sanity check? You may need to set up netconsole to capture the BUG_ON if you hit it. -- Jesse Barnes, Intel Open Source Technology Center diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 29743de..d01f403 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2921,6 +2921,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) temp &= ~(TRANSB_DPLLB_SEL); temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); } else if (pipe == 2) { + BUG_ON(!IS_IVYBRIDGE(dev)); temp &= ~(TRANSC_DPLLB_SEL); temp |= (TRANSC_DPLL_ENABLE | transc_sel); } @@ -3114,6 +3115,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); break; case 2: + BUG_ON(!IS_IVYBRIDGE(dev)); /* C shares PLL A or B */ temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); break; @@ -3126,6 +3128,8 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) /* disable PCH DPLL */ if (!intel_crtc->no_pll) intel_disable_pch_pll(dev_priv, pipe); + else + BUG_ON(!IS_IVYBRIDGE(dev)); /* Switch from PCDclk to Rawclk */ reg = FDI_RX_CTL(pipe); @@ -5787,6 +5791,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, udelay(150); } } else { + BUG_ON(!IS_IVYBRIDGE(dev)); + if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) && fp == I915_READ(PCH_FP0(0))) { intel_crtc->use_pll_a = true;
signature.asc
Description: PGP signature
_______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
