From: Eugeni Dodonov <eugeni.dodo...@intel.com>
Simplify the code and cache-related parameters handling, and prepare to
export them to userspace in subsequent patches.
Signed-off-by: Eugeni Dodonov <eugeni.dodo...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 10 ++--------
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
include/drm/i915_drm.h | 8 ++++++++
4 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index abbbf32..45b3f5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -737,12 +737,6 @@ typedef struct drm_i915_private {
atomic_t forcewake_count;
} drm_i915_private_t;
-enum i915_cache_level {
- I915_CACHE_NONE,
- I915_CACHE_LLC,
- I915_CACHE_LLC_MLC, /* gen6+ */
-};
-
struct drm_i915_gem_object {
struct drm_gem_object base;
@@ -1213,13 +1207,13 @@ i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev,
int tiling_mode);
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
- enum i915_cache_level cache_level);
+ uint32_t cache_level);
/* i915_gem_gtt.c */
void i915_gem_restore_gtt_mappings(struct drm_device *dev);
int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
- enum i915_cache_level cache_level);
+ uint32_t cache_level);
void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
/* i915_gem_evict.c */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fb69337..dccec77 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2949,7 +2949,7 @@ i915_gem_object_set_to_gtt_domain(struct
drm_i915_gem_object *obj, bool write)
}
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
- enum i915_cache_level cache_level)
+ uint32_t cache_level)
{
int ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6042c5e..d556dc8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -31,7 +31,7 @@
/* XXX kill agp_type! */
static unsigned int cache_level_to_agp_type(struct drm_device *dev,
- enum i915_cache_level cache_level)
+ uint32_t cache_level)
{
switch (cache_level) {
case I915_CACHE_LLC_MLC:
@@ -117,7 +117,7 @@ int i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj)
}
void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
- enum i915_cache_level cache_level)
+ uint32_t cache_level)
{
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 28c0d11..e9f1cf4 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -844,4 +844,12 @@ struct drm_intel_overlay_attrs {
__u32 gamma5;
};
+
+/**
+ * Cache level definitions
+ */
+#define I915_CACHE_NONE 0
+#define I915_CACHE_LLC 1
+#define I915_CACHE_LLC_MLC 2
+
#endif /* _I915_DRM_H_ */
--
1.7.7.4
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