On Thu, 10 Nov 2011 14:18:07 +0100, Daniel Vetter <daniel.vet...@ffwll.ch> wrote: > We have to do this manually. Somebody had a Great Idea. > > Signed-Off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
People playing with this when not strictly required is scary to me.
Manually swizzling was a world of hurt. I got to play with things like
"when the management engine is enabled, it carves out the top N MB of
one of the dimms, and the corresponding N MB of the other dimm doesn't
get swizzled, and you lose".
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c
> b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index 861223b..af0a2fc 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -93,8 +93,20 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>
> if (INTEL_INFO(dev)->gen >= 6) {
> - swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> - swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> + uint32_t dimm_c0, dimm_c1;
> + dimm_c0 = I915_READ(MAD_DIMM_C0);
> + dimm_c1 = I915_READ(MAD_DIMM_C1);
> + dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_A_SIZE_MASK;
> + dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_A_SIZE_MASK;
> + /* Enable swizzling when the channels are populated with
> + * identically sized dimms. */
> + if (dimm_c0 == dimm_c1) {
> + swizzle_x = I915_BIT_6_SWIZZLE_9_10;
> + swizzle_y = I915_BIT_6_SWIZZLE_9;
> + } else {
> + swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> + swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> + }
> } else if (IS_GEN5(dev)) {
> /* On Ironlake whatever DRAM config, GPU always do
> * same swizzling setup.
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0a0b6b1..a62fa95 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -327,6 +327,8 @@
> #define ARB_MODE 0x04030
> #define ARB_MODE_SWIZZLE_SNB (1<<4)
> #define ARB_MODE_SWIZZLE_IVB (1<<5)
> +#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x)
> +#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x)
> #define RENDER_HWS_PGA_GEN7 (0x04080)
> #define BSD_HWS_PGA_GEN7 (0x04180)
> #define BLT_HWS_PGA_GEN7 (0x04280)
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