If the firmware did not initialize the backlight PWM registers, set up a default PWM frequency of 200 Hz. This is determined using the following formula:
freq = refclk / (128 * pwm_max) The PWM register allows the max PWM value to be set. So we want to use the formula, where freq = 200: pwm_max = refclk / (128 * freq) This patch will, in the case of missing PWM register initialization values, look for the reference clock frequency. Based on that, it sets an appropriate max PWM value for a frequency of 200 Hz. If no refclk frequency is found, the max PWM will be zero, which results in no change to the PWM registers. Signed-off-by: Simon Que <s...@chromium.org> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_panel.c | 32 +++++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5d5def7..a832028 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3275,6 +3275,7 @@ #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) #define BLC_PWM_PCH_CTL2 0xc8254 +#define BLC_PWM_PCH_FREQ_SHIFT 16 #define PCH_PP_STATUS 0xc7200 #define PCH_PP_CONTROL 0xc7204 diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index f15388c..4bf2bde 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -32,6 +32,10 @@ #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ +/* For computing default PWM settings */ +#define DEFAULT_BACKLIGHT_PWM_FREQ 200 +#define BACKLIGHT_REFCLK_DIVISOR 128 + void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, struct drm_display_mode *adjusted_mode) @@ -129,14 +133,32 @@ static int is_backlight_combination_mode(struct drm_device *dev) return 0; } +static u32 i915_get_default_max_backlight(struct drm_i915_private *dev_priv) +{ + u32 refclk_freq_mhz = 0; + if (HAS_PCH_SPLIT(dev_priv->dev)) + refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; + else if (dev_priv->lvds_use_ssc) + refclk_freq_mhz = dev_priv->lvds_ssc_freq; + + return refclk_freq_mhz * 1000000 / + (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ); +} + static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv) { u32 val; - - /* Restore the CTL value if it lost, e.g. GPU reset */ - + /* Restore the CTL value if it was lost, e.g. GPU reset */ + /* Use the default PWM max value if none is available. */ + /* Note that the default max value will only be used if there is no */ + /* value already initialized in the PWM register by the BIOS and */ + /* nothing saved in dev_priv. */ if (HAS_PCH_SPLIT(dev_priv->dev)) { val = I915_READ(BLC_PWM_PCH_CTL2); + if (dev_priv->saveBLC_PWM_CTL2 == 0 && val == 0) + dev_priv->saveBLC_PWM_CTL2 = + i915_get_default_max_backlight(dev_priv) << + BLC_PWM_PCH_FREQ_SHIFT; if (dev_priv->saveBLC_PWM_CTL2 == 0) { dev_priv->saveBLC_PWM_CTL2 = val; } else if (val == 0) { @@ -146,6 +168,10 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv) } } else { val = I915_READ(BLC_PWM_CTL); + if (dev_priv->saveBLC_PWM_CTL == 0 && val == 0) + dev_priv->saveBLC_PWM_CTL = + i915_get_default_max_backlight(dev_priv) << + BACKLIGHT_MODULATION_FREQ_SHIFT; if (dev_priv->saveBLC_PWM_CTL == 0) { dev_priv->saveBLC_PWM_CTL = val; dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); -- 1.7.3.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx