-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Am 06.09.2011 17:53, schrieb Keith Packard: > On Tue, 06 Sep 2011 15:11:12 +0200, Philipp Klaus Krause <p...@spth.de> wrote: > >> Here's the output from git-bisect: >> >> d74362c9e45689d8d7e3d4bcf6681c4358ef4f2e is the first bad commit >> commit d74362c9e45689d8d7e3d4bcf6681c4358ef4f2e >> Author: Keith Packard <kei...@keithp.com> >> Date: Thu Jul 28 14:47:14 2011 -0700 >> >> drm/i915: Flush other plane register writes >> >> Writes to the plane control register are buffered in the chip until a >> write to the DSPADDR (pre-965) or DSPSURF (post-965) register >> occurs. > > Makes me wonder if this is some interaction between page flipping and > frame buffer compression. Could you try turning it off with the > following kernel command line parameter? > > i915.i915_enable_fbc=0 >
The problem goes away with i915.i915_enable_fbc=0. I'll probably use that workaround until the issue is fixed. Philipp -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk5npvkACgkQbtUV+xsoLpoRPACguEnn/k9CBlIxXBNVhD1cO1/B tfEAn0udhnXMKnop2i1cEY8SztLN6RZT =TjEO -----END PGP SIGNATURE----- _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
