On Sun, 4 Sep 2011 17:35:00 +0200 Daniel Vetter <daniel.vet...@ffwll.ch> wrote:
> Quoting Chris Wilson's more concise description: > > "Ah I think I see the problem. As you point out we only mask the > current interrupt received, so that if we have a task pending (and so > IMR != 0) we actually unmask the pending interrupt and so could > receive it again before the tasklet is finally kicked off by the > grumpy scheduler." > > So we need the hw to issue PM interrupts A, B, A while the scheduler > is hating us and refuses to run the rps work item. On receiving PM > interrupt A we hit the > WARN because > > dev_priv->pm_iir == PM_A | PM_B > > Also add a posting read as suggested by Chris to ensure proper > ordering of the writes to PMIMR and PMIIR. Just in case somebody > weakens write ordering. > > Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch> Reviewed-by: Ben Widawsky <b...@bwidawsk.net> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
