On Tue, 9 Aug 2011 09:17:46 -0700, Jesse Barnes <jbar...@virtuousgeek.org> wrote:
> IVB uses the same interrupt reg layout as SNB, so add an IS_GEN7 to the
> interrupt debugfs file.
Here's a list of code which uses IS_GEN6 but is not also using
IS_GEN7 or IS_IVYBRIDGE. Seems like some of these should get fixed too:
i915_debugfs.c-499- seq_printf(m, "Interrupts received: %d\n",
i915_debugfs.c-500- atomic_read(&dev_priv->irq_received));
i915_debugfs.c-501- for (i = 0; i < I915_NUM_RINGS; i++) {
i915_debugfs.c:502: if (IS_GEN6(dev)) {
i915_debugfs.c-503- seq_printf(m, "Graphics Interrupt mask
(%s): %08x\n",
i915_debugfs.c-504- dev_priv->ring[i].name,
i915_debugfs.c-505-
I915_READ_IMR(&dev_priv->ring[i]));
--
i915_debugfs.c-646- seq_printf(m, " Size : %08x\n", ring->size);
i915_debugfs.c-647- seq_printf(m, " Active : %08x\n",
intel_ring_get_active_head(ring));
i915_debugfs.c-648- seq_printf(m, " NOPID : %08x\n",
I915_READ_NOPID(ring));
i915_debugfs.c:649: if (IS_GEN6(dev)) {
i915_debugfs.c-650- seq_printf(m, " Sync 0 : %08x\n",
I915_READ_SYNC_0(ring));
i915_debugfs.c-651- seq_printf(m, " Sync 1 : %08x\n",
I915_READ_SYNC_1(ring));
i915_debugfs.c-652- }
--
i915_debugfs.c-1531- struct drm_i915_private *dev_priv = dev->dev_private;
i915_debugfs.c-1532- int ret;
i915_debugfs.c-1533-
i915_debugfs.c:1534: if (!IS_GEN6(dev))
i915_debugfs.c-1535- return 0;
i915_debugfs.c-1536-
i915_debugfs.c-1537- ret = mutex_lock_interruptible(&dev->struct_mutex);
--
i915_debugfs.c-1548- struct drm_device *dev = inode->i_private;
i915_debugfs.c-1549- struct drm_i915_private *dev_priv = dev->dev_private;
i915_debugfs.c-1550-
i915_debugfs.c:1551: if (!IS_GEN6(dev))
i915_debugfs.c-1552- return 0;
i915_debugfs.c-1553-
i915_debugfs.c-1554- /*
--
i915_gem.c-3698- obj->base.write_domain = I915_GEM_DOMAIN_CPU;
i915_gem.c-3699- obj->base.read_domains = I915_GEM_DOMAIN_CPU;
i915_gem.c-3700-
i915_gem.c:3701: if (IS_GEN6(dev)) {
i915_gem.c-3702- /* On Gen6, we can have the GPU use the LLC
(the CPU
i915_gem.c-3703- * cache) for about a 10% performance
improvement
i915_gem.c-3704- * compared to uncached. Graphics requests
other than
--
i915_irq.c-567-
i915_irq.c-568- atomic_inc(&dev_priv->irq_received);
i915_irq.c-569-
i915_irq.c:570: if (IS_GEN6(dev))
i915_irq.c-571- bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
i915_irq.c-572-
i915_irq.c-573- /* disable master interrupt before clearing iir */
--
i915_irq.c-581- pm_iir = I915_READ(GEN6_PMIIR);
i915_irq.c-582-
i915_irq.c-583- if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
i915_irq.c:584: (!IS_GEN6(dev) || pm_iir == 0))
i915_irq.c-585- goto done;
i915_irq.c-586-
i915_irq.c-587- if (HAS_PCH_CPT(dev))
--
i915_irq.c-636- i915_handle_rps_change(dev);
i915_irq.c-637- }
i915_irq.c-638-
i915_irq.c:639: if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
i915_irq.c-640- /*
i915_irq.c-641- * IIR bits should never already be set because IMR
should
i915_irq.c-642- * prevent an interrupt from being shown in IIR. The
warning
--
i915_irq.c-1646- I915_WRITE_CTL(ring, tmp);
i915_irq.c-1647- return true;
i915_irq.c-1648- }
i915_irq.c:1649: if (IS_GEN6(dev) &&
i915_irq.c-1650- (tmp & RING_WAIT_SEMAPHORE)) {
i915_irq.c-1651- DRM_ERROR("Kicking stuck semaphore on %s\n",
i915_irq.c-1652- ring->name);
--
i915_irq.c-1806- I915_WRITE(GTIIR, I915_READ(GTIIR));
i915_irq.c-1807- I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
i915_irq.c-1808-
i915_irq.c:1809: if (IS_GEN6(dev))
i915_irq.c-1810- render_irqs =
i915_irq.c-1811- GT_USER_INTERRUPT |
i915_irq.c-1812- GT_GEN6_BSD_USER_INTERRUPT |
--
i915_suspend.c-820-
i915_suspend.c-821- if (IS_IRONLAKE_M(dev))
i915_suspend.c-822- ironlake_disable_drps(dev);
i915_suspend.c:823: if (IS_GEN6(dev))
i915_suspend.c-824- gen6_disable_rps(dev);
i915_suspend.c-825-
i915_suspend.c-826- /* Cache mode state */
--
i915_suspend.c-878- intel_init_emon(dev);
i915_suspend.c-879- }
i915_suspend.c-880-
i915_suspend.c:881: if (IS_GEN6(dev)) {
i915_suspend.c-882- gen6_enable_rps(dev_priv);
i915_suspend.c-883- gen6_update_ring_freq(dev_priv);
i915_suspend.c-884- }
--
intel_display.c-1625- /* enable it... */
intel_display.c-1626- I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
intel_display.c-1627-
intel_display.c:1628: if (IS_GEN6(dev)) {
intel_display.c-1629- I915_WRITE(SNB_DPFC_CTL_SA,
intel_display.c-1630- SNB_CPU_FENCE_ENABLE |
obj->fence_reg);
intel_display.c-1631- I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
--
intel_display.c-2516- temp = I915_READ(reg);
intel_display.c-2517- temp &= ~FDI_LINK_TRAIN_NONE;
intel_display.c-2518- temp |= FDI_LINK_TRAIN_PATTERN_2;
intel_display.c:2519: if (IS_GEN6(dev)) {
intel_display.c-2520- temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
intel_display.c-2521- /* SNB-B */
intel_display.c-2522- temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
--
intel_display.c-8152- }
intel_display.c-8153- dev_priv->display.fdi_link_train =
ironlake_fdi_link_train;
intel_display.c-8154- dev_priv->display.init_clock_gating =
ironlake_init_clock_gating;
intel_display.c:8155: } else if (IS_GEN6(dev)) {
intel_display.c-8156- if (SNB_READ_WM0_LATENCY()) {
intel_display.c-8157- dev_priv->display.update_wm =
sandybridge_update_wm;
intel_display.c-8158- } else {
--
intel_dp.c-303- * clock divider.
intel_dp.c-304- */
intel_dp.c-305- if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
intel_dp.c:306: if (IS_GEN6(dev))
intel_dp.c-307- aux_clock_divider = 200; /* SNB eDP input clock
at 400Mhz */
intel_dp.c-308- else
intel_dp.c-309- aux_clock_divider = 225; /* eDP input clock at
450Mhz */
--
intel_dp.c-312- else
intel_dp.c-313- aux_clock_divider = intel_hrawclk(dev) / 2;
intel_dp.c-314-
intel_dp.c:315: if (IS_GEN6(dev))
intel_dp.c-316- precharge = 3;
intel_dp.c-317- else
intel_dp.c-318- precharge = 5;
--
intel_dp.c-1375- for (;;) {
intel_dp.c-1376- /* Use intel_dp->train_set[0] to set the
voltage and pre emphasis values */
intel_dp.c-1377- uint32_t signal_levels;
intel_dp.c:1378: if (IS_GEN6(dev) && is_edp(intel_dp)) {
intel_dp.c-1379- signal_levels =
intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
intel_dp.c-1380- DP = (DP &
~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
intel_dp.c-1381- } else {
--
intel_dp.c-1450- break;
intel_dp.c-1451- }
intel_dp.c-1452-
intel_dp.c:1453: if (IS_GEN6(dev) && is_edp(intel_dp)) {
intel_dp.c-1454- signal_levels =
intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
intel_dp.c-1455- DP = (DP &
~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
intel_dp.c-1456- } else {
And, a couple which appear to be using IS_IVYBRIDGE instead of IS_GEN7
for no particularly good reason:
i915_irq.c-1744-
i915_irq.c-1745- INIT_WORK(&dev_priv->hotplug_work,
i915_hotplug_work_func);
i915_irq.c-1746- INIT_WORK(&dev_priv->error_work, i915_error_work_func);
i915_irq.c:1747: if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
i915_irq.c-1748- INIT_WORK(&dev_priv->rps_work,
gen6_pm_rps_work);
i915_irq.c-1749-
i915_irq.c-1750- I915_WRITE(HWSTAM, 0xeffe);
i915_irq.c:1751: if (IS_GEN6(dev) || IS_GEN7(dev)) {
i915_irq.c-1752- /* Workaround stalls observed on Sandy Bridge
GPUs by
i915_irq.c-1753- * making the blitter command streamer generate
a
i915_irq.c-1754- * write to the Hardware Status Page for
--
i915_irq.c-2053-{
i915_irq.c-2054- dev->driver->get_vblank_counter =
i915_get_vblank_counter;
i915_irq.c-2055- dev->max_vblank_count = 0xffffff; /* only 24 bits of
frame count */
i915_irq.c:2056: if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) ||
IS_IVYBRIDGE(dev)) {
i915_irq.c-2057- dev->max_vblank_count = 0xffffffff; /* full 32
bit counter */
i915_irq.c-2058- dev->driver->get_vblank_counter =
gm45_get_vblank_counter;
i915_irq.c-2059- }
--
keith.pack...@intel.com
pgppK2Xxp2fhH.pgp
Description: PGP signature
_______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
