On Wed, 20 Jul 2011 11:08:51 -0400
Adam Jackson <a...@redhat.com> wrote:
> Some active adaptors (VGA usually) only have two lanes at 2.7GHz.
> That's a maximum pixel clock of 144MHz at 8bpc, but 192MHz at 6bpc.
>
> Signed-off-by: Adam Jackson <a...@redhat.com>
> ---
>
> Patch is against drm-intel-next. Not even compile-tested yet, just
> looking for feedback. I _think_ the pre-gen5 path is right, the GM45 doc
> makes it sound like the bpc and dither bits only affect DP.
Yeah, it would be good to have this.
> + /* default to 8bpc */
> + pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
> + if (is_dp) {
> + if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
> + pipeconf |= PIPECONF_BPP_6 |
> + PIPECONF_DITHER_EN |
> + PIPECONF_DITHER_TYPE_ST1;
> + }
> + }
> +
> dpll |= DPLL_VCO_ENABLE;
Maybe this part would be cleaner if you added G4x support to
choose_pipe_bpp_dither and called it here instead?
--
Jesse Barnes, Intel Open Source Technology Center
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