The BSpec says that the GTIMR is not to be used for masking
interrupts.  Regardless, writing one register should be better than
writing two registers.

Signed-off-by: Eric Anholt <e...@anholt.net>
---
 drivers/gpu/drm/i915/i915_irq.c         |   19 +++++++++++++----
 drivers/gpu/drm/i915/intel_ringbuffer.c |   32 +++++++++---------------------
 2 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b79619a..0f8af27 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1782,21 +1782,30 @@ int ironlake_irq_postinstall(struct drm_device *dev)
        I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
        POSTING_READ(DEIER);
 
-       dev_priv->gt_irq_mask = ~0;
-
        I915_WRITE(GTIIR, I915_READ(GTIIR));
-       I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 
-       if (IS_GEN6(dev))
+       if (IS_GEN6(dev)) {
                render_irqs =
                        GT_USER_INTERRUPT |
                        GT_GEN6_BSD_USER_INTERRUPT |
                        GT_BLT_USER_INTERRUPT;
-       else
+
+               /* The GTIMR is not supposed to be used for command streamer
+                * interrupt events.  They are masked out in the per-ring
+                * interrupt masks.
+                */
+               dev_priv->gt_irq_mask = ~render_irqs;
+       } else {
                render_irqs =
                        GT_USER_INTERRUPT |
                        GT_PIPE_NOTIFY |
                        GT_BSD_USER_INTERRUPT;
+
+               dev_priv->gt_irq_mask = ~0;
+       }
+
+       I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
+
        I915_WRITE(GTIER, render_irqs);
        POSTING_READ(GTIER);
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 95c4b14..c6c4d23 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -621,7 +621,7 @@ ring_add_request(struct intel_ring_buffer *ring,
 }
 
 static bool
-gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
+gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 rflag)
 {
        struct drm_device *dev = ring->dev;
        drm_i915_private_t *dev_priv = dev->dev_private;
@@ -633,7 +633,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 
gflag, u32 rflag)
        if (ring->irq_refcount++ == 0) {
                ring->irq_mask &= ~rflag;
                I915_WRITE_IMR(ring, ring->irq_mask);
-               ironlake_enable_irq(dev_priv, gflag);
+               POSTING_READ(RING_IMR(ring->mmio_base));
        }
        spin_unlock(&ring->irq_lock);
 
@@ -641,7 +641,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 
gflag, u32 rflag)
 }
 
 static void
-gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
+gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 rflag)
 {
        struct drm_device *dev = ring->dev;
        drm_i915_private_t *dev_priv = dev->dev_private;
@@ -650,7 +650,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 
gflag, u32 rflag)
        if (--ring->irq_refcount == 0) {
                ring->irq_mask |= rflag;
                I915_WRITE_IMR(ring, ring->irq_mask);
-               ironlake_disable_irq(dev_priv, gflag);
+               POSTING_READ(RING_IMR(ring->mmio_base));
        }
        spin_unlock(&ring->irq_lock);
 }
@@ -1105,33 +1105,25 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer 
*ring,
 static bool
 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
 {
-       return gen6_ring_get_irq(ring,
-                                GT_USER_INTERRUPT,
-                                GEN6_RENDER_USER_INTERRUPT);
+       return gen6_ring_get_irq(ring, GEN6_RENDER_USER_INTERRUPT);
 }
 
 static void
 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
 {
-       return gen6_ring_put_irq(ring,
-                                GT_USER_INTERRUPT,
-                                GEN6_RENDER_USER_INTERRUPT);
+       return gen6_ring_put_irq(ring, GEN6_RENDER_USER_INTERRUPT);
 }
 
 static bool
 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
 {
-       return gen6_ring_get_irq(ring,
-                                GT_GEN6_BSD_USER_INTERRUPT,
-                                GEN6_BSD_USER_INTERRUPT);
+       return gen6_ring_get_irq(ring, GEN6_BSD_USER_INTERRUPT);
 }
 
 static void
 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
 {
-       return gen6_ring_put_irq(ring,
-                                GT_GEN6_BSD_USER_INTERRUPT,
-                                GEN6_BSD_USER_INTERRUPT);
+       return gen6_ring_put_irq(ring, GEN6_BSD_USER_INTERRUPT);
 }
 
 /* ring buffer for Video Codec for Gen6+ */
@@ -1155,17 +1147,13 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
 static bool
 blt_ring_get_irq(struct intel_ring_buffer *ring)
 {
-       return gen6_ring_get_irq(ring,
-                                GT_BLT_USER_INTERRUPT,
-                                GEN6_BLITTER_USER_INTERRUPT);
+       return gen6_ring_get_irq(ring, GEN6_BLITTER_USER_INTERRUPT);
 }
 
 static void
 blt_ring_put_irq(struct intel_ring_buffer *ring)
 {
-       gen6_ring_put_irq(ring,
-                         GT_BLT_USER_INTERRUPT,
-                         GEN6_BLITTER_USER_INTERRUPT);
+       gen6_ring_put_irq(ring, GEN6_BLITTER_USER_INTERRUPT);
 }
 
 
-- 
1.7.5.1

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