On Fri, 22 Apr 2011 22:34:46 +0100
Chris Wilson <ch...@chris-wilson.co.uk> wrote:
> Despite the fixes in 548f245ba6a31 (drm/i915: fix per-pipe reads after
> "cleanup"), we missed one neighbouring read that was mistakenly replaced
> with the reg value in 9db4a9c (drm/i915: cleanup per-pipe reg usage).
> This was preventing us from correctly determining the mode the BIOS left
> the panel in for machines that neither have an OpRegion nor access to
> the VBT, (e.g. the EeePC 700).
>
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Jesse Barnes <jbar...@virtuousgeek.org>
> Cc: sta...@kernel.org
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e7822a6..aef6c6b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5799,9 +5799,9 @@ static int intel_crtc_clock_get(struct drm_device *dev,
> struct drm_crtc *crtc)
> intel_clock_t clock;
>
> if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
> - fp = FP0(pipe);
> + fp = I915_READ(FP0(pipe));
> else
> - fp = FP1(pipe);
> + fp = I915_READ(FP1(pipe));
>
> clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
> if (IS_PINEVIEW(dev)) {
Better, thanks.
Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
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