Older chipsets do not support snooping (i.e. cache sharing between the
CPU and GPU) on tiled surfaces. So prevent userspace from being silly
should we one day expose the ability to change cache levels from
userspace.
It does enforce a strict ordering for mode changing though. So in order
to change a buffer to snooped, the driver has to clear any tiling first
and then change the cache level. This is consistent with how we flush
and update the PTEs and seems a reasonable imposition on the driver.
Deferring the check until use, whilst providing flexibilty here, implies
forcing extra unbinds and a more complicated error message from, for
example, execbuffer.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++
drivers/gpu/drm/i915/i915_gem_tiling.c | 9 +++++++++
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1f57f99..46b63c3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3053,6 +3053,14 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
if (obj->cache_level == cache_level)
return 0;
+ if (INTEL_INFO(obj->base.dev)->gen < 6 &&
+ obj->tiling_mode != I915_TILING_NONE &&
+ cache_level != I915_CACHE_NONE) {
+ DRM_DEBUG("can not enable snooping on a tiled surface, "
+ "it must be linear for pre-SandyBridge chipsets\n");
+ return -EINVAL;
+ }
+
if (obj->pin_count) {
DRM_DEBUG("can not change the cache level of pinned objects\n");
return -EBUSY;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c
b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 281ad3d..ca69fd4 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -331,6 +331,14 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
}
mutex_lock(&dev->struct_mutex);
+ if (INTEL_INFO(dev)->gen < 6 &&
+ args->tiling_mode != I915_TILING_NONE &&
+ obj->cache_level != I915_CACHE_NONE) {
+ DRM_DEBUG("can't not set a tiling mode on snooped memory,"
+ "it must be linear for pre-SandyBridge chipsets\n");
+ ret = -EINVAL;
+ goto err;
+ }
if (args->tiling_mode != obj->tiling_mode ||
args->stride != obj->stride) {
/* We need to rebind the object if its current allocation
@@ -360,6 +368,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
}
}
/* we have to maintain this existing ABI... */
+err:
args->stride = obj->stride;
args->tiling_mode = obj->tiling_mode;
drm_gem_object_unreference(&obj->base);
--
1.7.4.1
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