On Wed, 30 Mar 2011 18:16:11 +0100, Chris Wilson <ch...@chris-wilson.co.uk>
wrote:
> On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt <e...@anholt.net> wrote:
> > On Wed, 30 Mar 2011 08:09:47 +0100, Chris Wilson <ch...@chris-wilson.co.uk>
> > wrote:
> > > The series looks really good, only one quibble below.
> > >
> > > On Tue, 29 Mar 2011 16:59:53 -0700, Eric Anholt <e...@anholt.net> wrote:
> > > > +int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
> > > > + enum i915_cache_level cache_level)
> > > > + if (cache_level == I915_CACHE_NONE) {
> > > > + /* If we're coming frm LLC cached, then we haven't
> > > > + * actually been tracking whether the data is in the
> > > > + * CPU cache or not, since we only allow one bit set
> > > > + * in obj->write_domain. Just set it to the CPU cache
> > > > + * for now.
> > > > + */
> > > > + BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
> > > > + obj->base.write_domain = I915_GEM_DOMAIN_CPU;
> > > > + }
> > >
> > > [We can rearrange the code to convert the BUG_ON into a
> > > if (WARN_ON()) return -EBUSY;.]
> > >
> > > I think this is overkill, at least by my interpretation of the old BLT
> > > docs which imply that cache line invalidation (both CPU and GPU) is done
> > > for snooped PTEs on MI_FLUSH.
> >
> > And what about a CPU write through the GTT?
>
> Even on SNB these are still UC. And we should try hard not to, as the
> specs give dire warnings about writing to snooped PTEs through the GTT.
> (Since we will bypass the caches with the write, aiui, and cause
> confusion.)Oh, wow. That's really bad. Reject this series if so. If true, then we need to be accurately tracking the CPU write domain. Mapping for GTT would need to actually clflush, and we'd need to clflush to read GTT-written data. On the other hand, I'm surprised things survived the testing I've done if that's true, given that we're surely GTT pwriting the batchbuffer data in, and then reading them through LLC. I would expect to pull in a bunch of zeroes in place of actual commands. Were you perhaps referring to pre-gen6 chipsets?
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