On Mon, 4 Oct 2010 15:13:17 +0200 Jan-Hendrik Zab <j...@jhz.name> wrote:
> On 03/10/10 08:04 -0700, Jesse Barnes wrote: > > On Thu, 2 Sep 2010 23:37:26 +0800 > > Zhenyu Wang <zhen...@linux.intel.com> wrote: > [snip] > > > Adam, I believe this one causes regression on PCH eDP port as > > > for bug 27220. It changes behavior in mode_set path to program > > > FDI link properly. > > > > > > I think above part should be reverted for .36 kernel. What's your > > > idea? > > > > > > Thanks Yakui to remind me about this recent change. > > > > Did PCH eDP ever work? I'll try going back to a kernel before this > > change, but current code definitely seems broken (we get never try to > > get a real clock value for PCH eDP, and I don't think we program the > > transcoder regs at all). > > > > Even with those fixed though (among other things), I haven't been able > > to get my Vaio with switchable graphics working. Which platforms did > > you have working, and what changeset is most likely to work? > > There were a few revisions that worked fine with a Vaio VPCZ11C5E, > among them: > > - 36e83a187ca7517e9bdce7148b1c2c27661ef38f > - a2757b6fab6dee3dbf43bdb7d7226d03747fbdb1 > > But I was unable to bisect the problem properly until now and bug 29414 > isn't exactly helping either. First commit adds eDP on PCH support but doesn't work for me. Second looks unrelated on ILK (SNB caching bits commit). -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
