[Intel-gfx] [PATCH 1/2] drm/i915/suspend: Flush register writes before busy-waiting.

[Chris Wilson]

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_suspend.c |   27 ++++++++++++++++++---------
 1 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c 
b/drivers/gpu/drm/i915/i915_suspend.c
index 6e20252..05acc26 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -395,16 +395,20 @@ static void i915_restore_modeset_reg(struct drm_device 
*dev)
        if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
                I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
                           ~DPLL_VCO_ENABLE);
-               DRM_UDELAY(150);
+               POSTING_READ(dpll_a_reg);
+               udelay(150);
        }
        I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
        I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
        /* Actually enable it */
        I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
-       DRM_UDELAY(150);
-       if (IS_I965G(dev) && !IS_IRONLAKE(dev))
+       POSTING_READ(dpll_a_reg);
+       udelay(150);
+       if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
                I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
-       DRM_UDELAY(150);
+               POSTING_READ(DPLL_A_MD);
+       }
+       udelay(150);
 
        /* Restore mode */
        I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
@@ -460,16 +464,20 @@ static void i915_restore_modeset_reg(struct drm_device 
*dev)
        if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
                I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
                           ~DPLL_VCO_ENABLE);
-               DRM_UDELAY(150);
+               POSTING_READ(dpll_b_reg);
+               udelay(150);
        }
        I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
        I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
        /* Actually enable it */
        I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
-       DRM_UDELAY(150);
-       if (IS_I965G(dev) && !IS_IRONLAKE(dev))
+       POSTING_READ(dpll_b_reg);
+       udelay(150);
+       if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
                I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
-       DRM_UDELAY(150);
+               POSTING_READ(DPLL_B_MD);
+       }
+       udelay(150);
 
        /* Restore mode */
        I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
@@ -730,7 +738,8 @@ void i915_restore_display(struct drm_device *dev)
        I915_WRITE(VGA0, dev_priv->saveVGA0);
        I915_WRITE(VGA1, dev_priv->saveVGA1);
        I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
-       DRM_UDELAY(150);
+       POSTING_READ(VGA_PD);
+       udelay(150);
 
        i915_restore_vga(dev);
 }
-- 
1.7.1

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