On Wed,  4 Aug 2010 21:22:10 +0200, Daniel Vetter <daniel.vet...@ffwll.ch> 
wrote:
> My i855GM suffers from a 80k/s interrupt storm without this.
> So add 2nd gen to the list of things that don't like more than
> one outstanding pageflip request.
> 
> Furthermore I've changed the busy loop into a ringbuffer wait.
> Busy-loops that don't check whether the chip died are simply evil.
> And performance should actually improve, because there's usually
> a decent amount of rendering queued on the gpu, hopefully rendering
> that MI_WAIT into a noop by the time it's executed.
> 
> The current code holds dev->struct_mutex while executing this loop,
> hence stalling all other gem activity anyway.
> 
> Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
> Cc: sta...@kernel.org
> ---
>  drivers/gpu/drm/i915/intel_display.c |   13 ++++++++-----
>  1 files changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 8135ee0..7b6035e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4916,14 +4916,17 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>       work->pending_flip_obj = obj;
>  
>       if (intel_crtc->plane)
> -             flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
> +             flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
>       else
> -             flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
> +             flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
>  
>       /* Wait for any previous flip to finish */
> -     if (IS_GEN3(dev))
> -             while (I915_READ(ISR) & flip_mask)
> -                     ;
> +     if (IS_GEN3(dev) || IS_GEN2(dev)) {
> +             BEGIN_LP_RING(2);
> +             OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
> +             OUT_RING(0);
> +             ADVANCE_LP_RING();
> +     }

If you move the if(intel_crtc->plane) inside the gen2/3 block, then I'll
test it on my netbooks. :)

Starting to look like intel_overlay.c ;-)

-- 
Chris Wilson, Intel Open Source Technology Centre
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