We're programming an 8-bit palette, so ensure we set the hardware
up appropriately. Also, rename the palreg variable pal_reg for more
consistency with the rest of this file.
---
drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++++----
1 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4e5e688..006e5a5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3430,7 +3430,10 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
+ int pipe = intel_crtc->pipe;
+ int pal_reg = (pipe == 0) ? PALETTE_A : PALETTE_B;
+ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
+ int pipeconf = I915_READ(pipeconf_reg);
int i;
/* The clocks have to be on to load the palette. */
@@ -3439,11 +3442,16 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
/* use legacy palette for Ironlake */
if (IS_IRONLAKE(dev))
- palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
- LGC_PALETTE_B;
+ pal_reg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
+ LGC_PALETTE_B;
+
+ /* Switch to 8-bit gamma mode */
+ pipeconf &= ~PIPEACONF_GAMMA;
+ I915_WRITE(pipeconf_reg, pipeconf);
+ I915_READ(pipeconf_reg);
for (i = 0; i < 256; i++) {
- I915_WRITE(palreg + 4 * i,
+ I915_WRITE(pal_reg + 4 * i,
(intel_crtc->lut_r[i] << 16) |
(intel_crtc->lut_g[i] << 8) |
intel_crtc->lut_b[i]);
--
1.7.0.4
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