I feel it’s important how to use the instruction and it’s pros and cons. I am not sure how important speed of instructions or width , halfword or full word are that pressing of an issue with today’s processors, but that’s my opinion.
Scott On Wed, Aug 28, 2019 at 11:18 AM scott Ford <idfli...@gmail.com> wrote: > Charles, > > Exactly, what is being done under the covers, i.e; microcode etc .. > > Scott > > On Wed, Aug 28, 2019 at 10:49 AM Tony Harminc <t...@harminc.net> wrote: > >> On Wed, 28 Aug 2019 at 09:59, Charles Mills <charl...@mcn.org> wrote: >> >> > In answer to your question, I guess the answer is no. There is a DAT >> "facility" (some of us remember when there was a DAT box!) but no, there is >> no named "PC facility" any more than there is a "BAL facility." It's just >> part of the processors. >> >> It's arguable that ASN translation is (usually) the part of the >> architecture that corresponds best to DAT in the context of PC and PR >> instruction processing. But not all PCs invoke ASN translation, and >> those that do do it a bit differently than how it is described in >> Chapter 3. >> >> But really, as Binyamin said, the excruciating details of what PC >> *does* are covered in the POPS, both under the PC instruction itself, >> and in Chapter 5 in the section "Stacking Process" under "Linkage >> Stack Operations". >> >> Tony H. >> >> ---------------------------------------------------------------------- >> For IBM-MAIN subscribe / signoff / archive access instructions, >> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN >> > -- > Scott Ford > IDMWORKS > z/OS Development > -- Scott Ford IDMWORKS z/OS Development ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
