How about RUCSA (or CSA)?  Common memory addressable by all address
spaces but only used by affected address spaces.
https://www.ibm.com/docs/en/zos/2.4.0?topic=overview-virtual-storage-address-space-esa-extensions

On Wed, Sep 4, 2024 at 2:48 PM Rob Scott
<[email protected]> wrote:
>
> Alternatives to WAIT/POST include PAUSE/RELEASE and maybe when the waiter is 
> a server or resource-owning ASID using PC-ss to add the request to "resume" 
> to a server resident queue to be processed H=P=S by a queue-handler subtask.
>
> Rob Scott
> Rocket Software
>
> Get Outlook for Android<https://aka.ms/AAb9ysg>
> ________________________________
> From: IBM Mainframe Discussion List <[email protected]> on behalf of 
> Charles Mills <[email protected]>
> Sent: Wednesday, September 4, 2024 7:17:43 PM
> To: [email protected] <[email protected]>
> Subject: Re: POSTing a WAIT in another Address Space; POST ASCB= parameter; 
> S602 Abend
>
> EXTERNAL EMAIL
>
>
>
>
>
> Staying out of trouble with X-memory post is a tough assignment. Sad voice of 
> experience here: I am looking at a six-year-ago reprimand from IBM support 
> for making a mess in an LPAR with the x-memory post code in a vendor product 
> I wrote.
>
> Use IEAMSXMP! (Unless support for z/OS < V2R2 is necessary.)
>
> I would post code here but without a lot of context I don't think my IEAMSXMP 
> is very clear.
>
> If performance is important, consider bypassing the POST when possible with 
> CS. Here's how you do that:
>
>          L     R0,AV_QECB          Get contents of ECB
> *
> PostTryAgain EQU *
> *  If post bit is already on then no need to post again
> *  If wait bit is on then have to actually POST to release task
>          TMLH  R0,X'C000'          Is it waiting or already posted?
>          JNZ   IsWaitingOrPosted     Yes
>          LLILF R1,X'40000000'      Post bit and post code
>          CS    R0,R1,AV_QECB       Compare and swap to post ECB
>          JNZ   PostTryAgain          Failed, try again
>          J     CountPOSTs          Worked, account just like did a POST
> *
> IsWaitingOrPosted EQU *            Wait or Posted bit is on
>          TMLH  R0,X'8000'          Is anyone waiting?
> *                                    No, then (a.) no need to POST; and
>          JZ   AlreadyPosted          (b.) Post bit must already be on
> *
> *  Wait bit is on so need to do a real POST
> and here is where your IEAMSXMP would go
>
> Hope this helps.
> Charles
>
>
> On Wed, 4 Sep 2024 17:37:21 +0000, Richard Zierdt 
> <[email protected]> wrote:
>
> >Thanks, Rob, Tom.  Yes, Key 0 is dangerous, but documented as a requirement 
> >(for LINKAGE=BRANCH anyway).
> >I was unaware of IEAMSXMP (and TCBTOKEN, which extracts the target program's 
> >TTOKEN).
> >So I'm coding for those now.
> >BTW, the standard from of POST supports register notation and RX-type.  Rx 
> >does a LA - ST into the POST's parameter list, which means it's the address 
> >of the ASCB, not the ASCB itself.  I'll try L  Rx,ASCB  and  POST . . . 
> >ASCB=(Rx) and test that.
> >Nonetheless, avoiding Key 0 is better.   I'll reply later with results.
>
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-- 
Mike A Schwab, Springfield IL USA
Where do Forest Rangers go to get away from it all?

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