I know of other architectures where index registers are coupled with segment pointer registers, e.g., for MULTICS, and where there are load and store pointer instructions that operate on register pairs, and it seems like an obvious facility for AR mode. My concern is code density rather than atomicity, although that would be desirable.
-- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 עַם יִשְׂרָאֵל חַי נֵ֣צַח יִשְׂרָאֵ֔ל לֹ֥א יְשַׁקֵּ֖ר ________________________________________ From: IBM Mainframe Discussion List <[email protected]> on behalf of Tony Harminc <[email protected]> Sent: Wednesday, August 28, 2024 1:18 PM To: [email protected] Subject: Re: L/ST AR/GR pair? On Wed, 28 Aug 2024 at 13:01, Seymour J Metz <[email protected]> wrote: > Are there instructions to load and store both a general register and the > associated access register, or do you still need separate loads and > separate stores? > Well, LAE[Y], as has been discussed recently. But I assume you want to load arbitrarily different data into the GR and AR. And yes, those are LA-type instructions, not L-type. Are you also looking for atomicity of some sort? I don't think there's anything like PLO or Load Disjoint for ARs. Tony H. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
