On Fri, Sep 22, 2023 at 01:58:00PM -0400, Joseph Reichman wrote:
> I am posting my code in addition to some displays I captured as I am getting
> the feeling my IRB was not dispatched for some reason
>
> So here is the code in my STIMER routine from where I issue the SCHEDIRB
> pointing to the IQE generated by the CIRB
I don't see why you need the stimer routine. The description of
SCHEDIRB says that is for "directed IRB" where you specify your IRB
is to run before the specified RB.
> Here using LOOK is a display of the IRB Address 8AA7A8 don't know Why
> RBEPA has bit 0 a 0 looking at the RBOPSW it's a 0
> LAST CMD - 8AA7A8
{storage display text realligned..}
00000000_008AA7A8 >000077B8 00000000 010F404E 9FF01E81 *>.......... +.0.a*
00000000_008AA7B8 078D0000 9FF01E80 008AA80C 008FEA90 *.....0....y.....*
00000000_008AA7C8 00000001 FF735894 852CAB40 052CBB3F *.......me.. ....*
00000000_008AA7D8 808CACD0 00000000 008CACA8 008CACD0 *...........y....*
00000000_008AA7E8 008CACD8 00000000 008C9AB8 052CCB3E *...Q............*
00000000_008AA7F8 008CA2C0 008CA2C0 852CB72C 808FEA90 *..s...s.e.......*
00000000_008AA808 008AA80C 00000000 00026A6C 008AA7A8 *..y........%..xy*
00000000_008AA818 008E76D0 00000000 00000000 00000000 *................*
The RB mapping includes fields for all types of RBs: PRB, SVRB, IRB,
SIRB and perhaps for types & flavors which don't exist anymore (since
before MVT). A lot of these fields overlap as they aren't used at them
same time.
Looking at our IRB:
+0 (4) 000077B8 address of problem program save area
+8 (2) 010f length of RB in double words
+a (1) 40 is an IRB
+b (1) 4d ? bits about has IQE, don't return IQE
+c (4) 9ff01e81 rbepa, looks like low bit is flag bit for mode=defined
+10 (8) 078d0000 9ff01e80 -> psw
+18 (4) 008aa80c list orig for iqe
+60 (4) 008aa80c rbnexav => @ next avail IEQ
+64 (.) ..IQE..
The IQE: 00000000 00026A6C 008AA7A8 00000000
+0 (4) 00000000 link
+4 (4) 00026A6C IQEPARAM
+8 (4) 008AA7a8 IQEIRB
+c (4) 00000000 IQETCB
why isn't IQETCB set?
https://www.ibm.com/docs/en/zos/2.1.0?topic=routines-using-cirb-macro-initialize-irb
The same TCB needs to be used to allocate the storage for the IRB
and to free it, thus CIRB needs the TCB address in addition to
the TCB address in the IQE (task to run the IRB).
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