> On Monday, July 31, 2023 at 01:41:36 PM PDT, Tom Brennan
> <t...@tombrennansoftware.com> wrote:
> The AIU (Integrated Artificial Intelligence Accelerator Unit) is a
> portion of each chip in a z16, maybe about 1% of chip real estate, that
> contains something they call the "Matrix Compute Array" containing 128
> "Processor Tiles" (whatever those are). To me, those PT's make it look
> more like a GPU than FPU.
Matrix Compute Array makes more sense than simple computations. With FPUs being
multi-core, they could use a core to represent each entry in the matrix. This
makes it a little easier to understand how they are using it represent
selection criteria or concept correlation. GPT-4 had its definitions leaked and
from what I understood (could be very wrong), the first selection is based on
broad categories and filtered down from there. With enough horsepower, you can
solve any problem.
On Monday, July 31, 2023 at 01:41:36 PM PDT, Tom Brennan
<t...@tombrennansoftware.com> wrote:
The AIU (Integrated Artificial Intelligence Accelerator Unit) is a
portion of each chip in a z16, maybe about 1% of chip real estate, that
contains something they call the "Matrix Compute Array" containing 128
"Processor Tiles" (whatever those are). To me, those PT's make it look
more like a GPU than FPU. The AIU also contains controlling AI firmware
and has direct access to the chip's cache, something a PC graphics card
might have a bit of trouble doing.
On 7/31/2023 12:31 PM, Jon Perryman wrote:
> The current implementation of AI is based on mathematical calculations.
> Rather than PCs using an FPU, they use graphics cards with GPU for these
> calculations. I'm guessing that IBM uses FPUs which can reach speeds of 5
> exa-FLOPs. I have no clue how they are making the leap from computations to
> decision processing.
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