Hi Steve,
You wrote:
I'm still curious about the conditional trap instructions, e.g. LAT, CIT.
They have programming notes that imply they're intended for use in
try-blocks, or assert. I have no idea if any current compilers use them.
The COMPARE AND TRAP type instructions don't seem particularly
mysterious to me. They preform a test (compare) and either fall thru
if the test is false or fail with a PIC 0007-FF data exception
(0C7-FF at ESTAE time) if the test is true.
They have nothing to do the TRAP2 and TRAP4 instructions, and nothing
to do with whether or not the task's DUCT has a Trap Handler exit installed.
The "handler" for COMPARE AND TRAPs is your garden variety ESTAE (or
ESPIE) recovery routine.
The point of the COMPARE AND TRAP instructions is probably
pipelining. There is no branch that has to be predicted. The hardware
look-aheads can just presume execution will continue without
branching. If an interrupt occurs...
* (a) that's a very expensive event anyway,
* So (b) pipeline cache throwaways is not that much of an added burden.
The nature of the COMPARE AND TRAPs is such that the programmer is
going to use them in situations where the trap action (i.e. the PIC
0007-FF) will happen only rarely, thus making pipe-linking's
fall-thru assumptions almost always correct.
I'm not a compiler maven, but these days, with the hardware designers
and the compiler writers working hand in hand with each other, I'm
pretty sure the COMPARE AND TRAPs were created at the behest of the
compiler writers.
Dave Cole, Developer
[email protected] (personal)
[email protected] (business)
540-456-6518 (cell)
At 3/2/2023 09:29 AM, Steve Smith wrote:
I'm still curious about the conditional trap instructions, e.g. LAT, CIT.
They have programming notes that imply they're intended for use in
try-blocks, or assert. I have no idea if any current compilers use them.
sas
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