[email protected] (Shmuel Metz , Seymour J.) writes: > Only if you're talking about the same instruction mix. When one system > has instructions like MVCL and the other doesn't, MIPS truly means > "meaningless indication of processor speed". A comparison of FLOPS > ratings might be more meaningful, since the spread between the slowest > and the fastest operation isn't as large.
note that x86 BIPS ratings are number of iterations executing dhrystone benchmark compared to vax 780 assumed to be 1mip ... have no idea *real* instruction execution rate. past discussion in this thread http://www.garlic.com/~lynn/2012d.html#41 Layer 8: NASA unplugs last mainframe above also mentions i7-3960x is single socket/chip with approx. four times the BIPS rating of 80processor z196 max. configured 64processor z10 was claimed to be 30BIPS ... and that increased by 2/3rds to 50BIPS for 80processor z196. increase in processors from 64 to 80 can account for increase of 25%. tech articles claim the introduction of out-of-order execution for z196 accounts for another 20-25%. other misc. would then account for the remainder of the increase. note that out-of-order execution, branch prediction, speculative execution, etc have all been part of risc technology for decades. the recent generations of i86 processors have negated much of the risc performance advantage by moving to risc processors with hardware layer that translates i86 instructions to risc micro-ops. part of the issue is that cache miss delays (aka access to memory) counted in processor cycles are now compareable to 360-era disk access delays. multiprogramming/multitasking was introduced to give processors something to do while waiting for disk access. out-of-order execution and hyperthreading are comparable for modern technologies (keeping the processor units busy while waiting for stalled instruction access to memory). 370/195 allowed out-of-order execution with pipeline ... but stalled at conditional branch (having to wait to determine execution path that branch would take). normal codes ran about half peak rate on 370/195 (because of branch stalls) and there was proposal to do simulated multiprocessor (similar to modern hyperthread); two instruction streams, pair of PSWs, two sets of registers ... etc. ... trying to maintain to keep 370/195 running at peak processing rate. modern branch prediction and speculative execution ... will do out-of-order execution along one path (before branch condition is determined). If the branch prediction is wrong, the incorrectly executed instructions are undone ... and processing resumes along the correct path. recent post in this thread: http://www.garlic.com/~lynn/2012l.html#28 X86 server there was reference to older mainframe TPC benchmark ... there was some published work for z10 which was then prorated by 50/30 to give estimate for z196 ... as a means of making other thruput comparisons. -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
