On 17/05/2012 2:06 AM, Tom Marchant wrote:
On Tue, 15 May 2012 20:07:52 +0000, Robert Prins wrote:
maybe a 16-byte
three-instruction sequence like
003FC0 E310 DF10 0158 003120 | LY r1,<a1:d7952:l4>(,r13,7952)
003FC6 E300 1047 0015 003120 | LGH r0,_shadow20(,r1,71)
003FCC 4000 E064 003120 | STH r0,_shadow20(,r14,100)
is really faster than the simple 6-byte one-instruction sequence
0026D4 D2 01 7 064 6 047 MVC REPT_LINE.DATE.MONTH(2),REPT_LIST.DATE.MONTH
Not likely.
Address Generation Interlock (AGI) will cause the second instruction
to stall until the address is available in R1.
Tom,
I'm not sure if that's still true on z10/z196 processors which implement
AGI bypass.
http://www.ibmsystemsmag.com/CMSTemplates/IBMSystemsMag/Print.aspx?path=/mainframe/administrator/performance/cpu_pipeline
Apparently the worst case scenario is a load in 1 cycle. Load address
has been mitigated.
In addition, instruction cracking will, under some circumstances, cause
a z196 processor to execute a load and a store when a MVC instruction
is executed.
----------------------------------------------------------------------
For IBM-MAIN subscribe / signoff / archive access instructions,
send email to [email protected] with the message: INFO IBM-MAIN
