At least with z196 I think the cost of real memory in the processor is
low enough that you should be able to make a case to purchase more to
reduce or eliminate paging if it is a performance issue. We manage to
0% residency on local page data sets instead manage real storage
available "budget" by AFQA size. The instructions to do that paging
I/O take elapsed time, execute on general purpose processors, and the
cycle time out to cache in a storage processor is an order of magnitude
greater than reference to an old but paged in memory frame. Memory rich
environments don't have to be all that rich with real memory on z196 now
roughly 15% of the cost of what it was when IBM announced the mainframe
charter in 2003.
Best Regards,
Sam Knutson, GEICO
System z Team Leader
mailto:[email protected]
(office) 301.986.3574
(cell) 301.996.1318
"Think big, act bold, start simple, grow fast..."
-----Original Message-----
From: IBM Mainframe Discussion List [mailto:[email protected]] On
Behalf Of Vernooij, CP - SPLXM
Sent: Monday, February 13, 2012 2:37 AM
To: [email protected]
Subject: Re: Acceptable paging
Ron,
At the moment I only have ESSs, but we are going to new storage soon. We
expect everything to improve.
Kees.
"Ron Hawkins" <[email protected]> wrote in message
news:<00ad01cce88a$d99abf30$8cd03d90$@net>...
> Kees,
>
> Have you thought of putting your page datasets into Permacache (EMC)
or DCR
> (HDS).
>
> This would give you true SSD performance right on the channel, which
is
> better than the SAS HDD emulation variety.
>
> Ron
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