On Tue, 31 May 2011 18:10:11 -0400, Andy Coburn <[email protected]> wrote:
>The following is a snip from a program which I just ran on our Z10 whose
>characteristics are shown last below. The program first moved 65536 bytes
>from one location to another using MVCL and did this 1 million times. You'll
>see it took ~56 seconds. Then the same number of bytes were moved using 1
>million MVC loops. This took ~8 seconds. Finally, the same number of bytes
>were moved 1 million times using MVCLE.
> ...
>
Is this affected by operand alignment?
Extending the topic somewhat: I understand that (model
sensitive?) there's an enormous penalty for off-boundary
RX instructions. A frequent use of LH/STH might be
accessing RDWs where the programmer can't control the
alignment. So, assuming half the RDWs are misaligned, is
it best to:
LH and endure the penalty
or:
XR
IC
SLL
IC
or:
MVC to an aligned buffer
LH
In the latter two cases, is it better to test the
address and LH if even?
S/370's introduction of unaligned operations seems to be
contrary to the trend du jour toward RISC architecture.
-- gil
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