On Tuesday, June 9th, 2026 at 4:17 AM, Heime <[email protected]> wrote:
> On Tuesday, June 9th, 2026 at 12:06 AM, Paul Smith <[email protected]> wrote: > > > On Sun, 2026-06-07 at 08:57 +0000, Heime wrote: > > > I want to avoid passing using a variable like this > > > > > > make -f myfile.mk opt=--split=chapter > > > > > > Rather, I want a direct setting like thisn > > > > > > make -f myfile.mk -- --html --split=chapter > > > > > > And be able to pass all option to the command part of a > > > makefile rule. > > > > What you want to do is not possible. Make is not a general-purpose > > interpreter that allows makefiles to investigate and interpret its > > command-line arguments. > > > > The only thing you can do is write a shell script wrapper around make, > > that will parse the arguments and pass them to make using a variable > > assignment. --- Paul D. Smith Parsing options to makefile, arguments after -- end up considered either as variable assignments (if they contain an = symbol) or as targets to build. I'm not aware of a way for a Makefile to determine generically all the variables and targets specified as command-line arguments. Assignments end up in $(MAKEFLAGS) but that's it. I can’t think of many (or even any) shell script wrappers used for `make`. I thought to use something that behaves like a shell script, but using the `make` invocation syntax doesn’t bring much benefit anyway. Building something that looks like a typical command-line program, processing options and arguments, Make isn’t the right tool. If I'm going to use `make`, I should embrace its features instead of trying to work around them. How does one typically handle various options for gcc. Are there some makefile examples I can study that allow for various compiling options to be used?
