Hello,
I have a question about running two makefiles that both include the same
third makefile. The third, common, makefile generates a file – “outfile.h”.
As an input it takes a path to the output directory, and input files from
which to produce the generated output. Those two inputs are provided by the
first two makefiles. The generated “outfile.h” is used in the source of the
project1 and project2. I ran the “make” with “–j6” option.
Project1
Project2
makeFile1
in “makeFile1”:
OUTPUT_DIR = path1
INPUT_FILES = \
In_file1\
In_file2
include common_makefile
makeFile2
in “makeFile2”:
OUTPUT_DIR = path2
INPUT_FILES = \
In_file3\
In_file4
include common_makefile
common_makefile
in “common_makefile”:
ifndef _COMMON_MAKEFILE_
_COMMON_MAKEFILE_ = 1
OUT_FILE := $(OUTPUT_DIR)\outfile.h
OUT_FILE : INPUT_FILES
COMMAND
endif
In Project1:
Use “outfile.h”
Project2:
“Use outfile.h”
When I ran a script that calls those two makefiles close to each other, the
files are not generated. Though, I see the OUTPUT_DIR is created for
project2.
If I comment the “ ifndef _COMMON_MAKEFILE_ … endif” block in the
“common_makefile”, and ran the script again, then I get the generated
“outfile.h” in the OUTPUT_DIR for project2,
but the content of it tells me that it’s a file for project1. So, it seems,
some race condition is happening when accessing the common_makefile at the
same time. Is there a way to run the “common_makefile” sequentially, first,
for project1, and then, for project2? Thank you.
Tanya.
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