It says this: An example will illustrate this:
clean: FORCE rm $(objects) FORCE: Here the target ‘FORCE’ satisfies the special conditions, so the target clean that depends on it is forced to run its recipe. There is nothing special about the name ‘FORCE’, but that is one name commonly used this way. As you can see, using ‘FORCE’ this way has the same results as using ‘.PHONY: clean’. This may be at least mostly true for the particular case of the clean target, which is generally invoked explicitly. However, its not true for the common case of an object file that one wants to always rebuild. This Makefile: %.o: %.c cp $< $@ # Simulate compile #.PHONY: test.o test.o: FORCE FORCE: test.o: Makefile fooprog: test.o cp $< $@ # Simulate link Will always recompile test.c into test.o as it is, but if the test.o: FORCE and FORCE: rules are replaced with the .PHONY: test.o rule (commented out above), then test.o will never be built at all. I think the description in 4.7 goes too far in implying equivalency. Either it shouldn't say the two are equivalent, or it should be more careful to qualify that that they are equivalent only in the particular case of the explicitly invoked phony target which doesn't have additional dependencies expressed in other rules. Britton _______________________________________________ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/help-make