I’ve had some luck simply pretending the targets are implicit. See
sample makefile below and note that no use is made of the % pattern in
the prereqs.
% cat Makefile
.PHONY: all
all: axx bxx
a% b%: cxx dxx
touch $@
touch bxx
.PHONY: clean
clean:
$(RM) axx bxx
% make clean && make -j
rm -f axx bxx
touch axx
touch bxx
On Tue, Jan 19, 2016 at 1:56 AM, Phillip Lord
<phillip.l...@russet.org.uk> wrote:
>
>
> While writing a make file, I've just hit the situation where I need to
> write a rule of the form:
>
>
> a b c d e: x y z
> generate_abcde
>
>
> Unfortunately, this doesn't work as the semantics are equivalent to the
> rules where the targets are separate -- that is generate_abcde gets run
> multiple times.
>
> I've done some poking around, and found that a couple of solutions,
> either with pattern rules or otherwise by creating an intermediate file,
> as described here:
>
> http://lists.gnu.org/archive/html/help-make/2007-04/msg00021.html
>
> My understanding is that there is no other way to do this, but I was
> wondering why this was the case; would it be possible to support to make
> for this directly?
>
> Phil
>
> _______________________________________________
> Help-make mailing list
> Help-make@gnu.org
> https://lists.gnu.org/mailman/listinfo/help-make
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