Let me quote from the GNU make manual on the "eval function". It says:
The argument to the eval function is expanded, then the results of that
expansion are parsed as makefile syntax.
Now in this case, of $(eval include /path/to/file.mk)the two arguments to eval
are the keyword include & the fullpath of file.mk
Since there are no characters to be expanded here, so in essence it's a
constant. Hence the resultsbefore & after the expansion are the same & then
make performs the actions indicated by thearguments, which is including the
file into the current makefile.
So, FAPP these two syntaxes are identical in this case.
Also, eval is normally employed when the arguments to it contain varying things
to be able to showoff it's versatility.
-Rakesh
> Date: Wed, 22 Jul 2015 20:02:00 -0700
> Subject: using $eval to include other makefiles
> From: hkmo...@gmail.com
> To: help-make@gnu.org
>
> Hello,
>
> I've noticed multiple ways of including a Makefile within another Makefile.
> For example, one could directly include the Makefile:
>
> # Filename top.mk
> ...
> include /path/to/file.mk
>
> One could also use the $eval function to include the Makefile:
>
> # Filename: top.mk
> ...
> $(eval include /path/to/file.mk)
>
> Both work fine. What's the difference? Is there an optimal or preferred
> method?
>
> Thanks!
> Hiran
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