Hello everybody,
I'm facing a problem in the parser I'm writting for which I haven't found
any valuable help in any forum I tried.
To be brief, here is an extract of the code:
%union
{
int ival;
const char* sval;
};
%type<ival> .mode.
%%
formal_port_element
: .SIGNAL. {g_list_type = Parser::PORT;}
identifier_list
Colon {g_list_type = Parser::UNKNOWN;}
.mode. { design.portSpecs($4);}
type_mark
.constraint.
.BUS.
.VarAsgn__expression.
;
.mode.
:/*empty*/{ $$ = VHDLDefs::NONE;}
| IN { $$ = VHDLDefs::IN;}
| OUT { $$ = VHDLDefs::OUT;}
| INOUT { $$ = VHDLDefs::INOUT;}
| BUFFER { $$ = VHDLDefs::NONE;}
| LINKAGE { $$ = VHDLDefs::NONE;}
;
My error is the following : $4 of 'formal_port_element' has no declared
type.
Which seems strange to me as $4 is '.mode.' rule, which is typed <ival> and
every $$ = VHDLDefs::X actions in this rule are correct according to bison.
I tried with $1 to $8 to check if anything change and weirdly, with $6 the
code pass whereas $7 and $8 are 'out of range'.
Thanks for the time you might spend on this problem,
Olivier LAPORTE.
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