Hello, all.
I hope some one already faced this problem in past. Who can help, please?
My Verilog parser, generated by bison does not start a parse process. It
happend in bison 1.50, 1.875c and latest 2.4.3
But it works fine, when generated with bison 1.35 !!!
What has changed from 1.35 to 1.50?
*The problem:
*
Parser bison:
#define YYTRACE(str) fprintf(stderr, " <Yacc>%s\n", str);
%%
source_text :
{ YYTRACE("sorce_text:");
$$ = vl_description = vl_create_desc("stdin"); }
| source_text description {
YYTRACE("source_text: source_text description"); }
;
description : module
{ YYTRACE("description: module"); }
| primitive
{ YYTRACE("description: primitive"); }
;
...
...
Input file:
module upi_top ;
endmodule
When the parser runs it just print:
<Yacc>sorce_text:
and calls to *yyerror* procedure, when error_msg == "syntax error" and
yytext == "module"
I would be very thankful if some one could advise me how to start to debug
this case*.*
--
-Thanks
-Baruch
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