Hi Arseny, Remember it is no longer the number of conditionals or reads but rather the number of L1 cache misses and writes that cause multi-core cache coherency stalls that dominate performance typically today.
Even more importantly, signal handling is very slow, and often "late". You would have to 1) trap the page fault and context switch to the kernel, 2) context switch back to the signal handler, 3) context switch back to the kernel to allocate a page or change its protections, and then 4) context switch back to the original faulting code. You are looking at least 3 but usually 4 context switches; this will be much, much slower than using the Go allocator. -- You received this message because you are subscribed to the Google Groups "golang-nuts" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion visit https://groups.google.com/d/msgid/golang-nuts/c1794480-6738-4924-8708-b0bfe29af8d3n%40googlegroups.com.
