On Mon, Nov 28, 2011 at 2:36 PM, Pandu Poluan <pa...@poluan.info> wrote: > On Nov 29, 2011 2:02 AM, "Florian Philipp" <li...@binarywings.net> wrote: >> Am 28.11.2011 18:56, schrieb Michael Mol: >> > On Mon, Nov 28, 2011 at 11:46 AM, Pandu Poluan <pa...@poluan.info> >> > wrote: >> >> On Nov 28, 2011 10:38 PM, "Michael Mol" <mike...@gmail.com> wrote: >> >>> On Sun, Nov 27, 2011 at 7:54 PM, Pandu Poluan <pa...@poluan.info> >> >>> wrote: >> >>>> Won't file a bug report, though. I have a feeling that my bug report >> >>>> re: >> >>>> emerge failure will be marked WONTFIX thanks to the 'ricer special' >> >>>> CFLAGS >> >>> >> >>> The CFLAGS you showed me weren't any more ricer than "-O2 >> >>> -march=native". (I didn't know that -D_FORTIFY=2 came from gcc) >> >>> >> >>> They wouldn't have a leg to stand on... >> >>> >> >> >> >> Mine is: >> >> >> >> CFLAGS="-O2 -march=native -fomit-frame-pointer -floop-interchange >> >> -floop-strip-mine -floop-block -funsafe-math-optimizations >> >> -fexcess-precision=fast" >> >> >> >> If you tell me that's not a ricer's CFLAGS, then you've just made me a >> >> very >> >> happy cat :-) >> > >> > No, you've got some ugly flags in there. -fexcess-precision and >> > -funsafe-math-optimizations, in particular. (I must have been talking >> > to someone else last week; sorry, I'm terrible with names.) >> > >> >> I doubt -fexcess-precision=fast does anything at all. Pandu uses an >> AMD64 system, right? Then you have -mfpmath=sse set per default and SSE >> does not have excess precision issues (that's just for the old x87 FPU). > > I use Intel boxes, unfortunately.
Are you using a 64-bit x86-derived system? Same difference in this context. AMD hit the market with a good 64-bit x86-based ISA first, and devs started calling it AMD64 then. That's mostly stuck even after Intel released a mostly-compatible competitor, EM64T. -- :wq
