commit: 5c3b5e006cbd915252a6dc345940e824f0275af9
Author: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org>
AuthorDate: Sun Feb 27 15:45:43 2022 +0000
Commit: Andreas K. Hüttel <dilfridge <AT> gentoo <DOT> org>
CommitDate: Sun Feb 27 15:45:43 2022 +0000
URL: https://gitweb.gentoo.org/proj/catalyst.git/commit/?id=5c3b5e00
arch: Add riscv64 lp64d musl definition
Signed-off-by: Andreas K. Hüttel <dilfridge <AT> gentoo.org>
catalyst/arch/riscv.py | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/catalyst/arch/riscv.py b/catalyst/arch/riscv.py
index 1fb2c69b..d7b76c37 100644
--- a/catalyst/arch/riscv.py
+++ b/catalyst/arch/riscv.py
@@ -23,6 +23,12 @@ class arch_rv64_lp64d(generic_riscv):
def __init__(self,myspec):
generic_riscv.__init__(self,myspec)
+class arch_rv64_lp64d_musl(generic_riscv):
+ "builder class for rv64_lp64d_musl"
+ def __init__(self,myspec):
+ generic_riscv.__init__(self,myspec)
+ self.settings["CHOST"]="riscv64-gentoo-linux-musl"
+
class arch_rv64_lp64(generic_riscv):
"builder class for rv64_lp64"
def __init__(self,myspec):
@@ -47,6 +53,7 @@ def register():
"riscv" : arch_riscv,
"rv64_multilib" : arch_rv64_multilib,
"rv64_lp64d" : arch_rv64_lp64d,
+ "rv64_lp64d_musl" : arch_rv64_lp64d_musl,
"rv64_lp64" : arch_rv64_lp64,
"rv32_ilp32d" : arch_rv32_ilp32d,
"rv32_ilp32" : arch_rv32_ilp32
