commit: 26563a34c895bf0923dee40f0bc4cfddbd1a6d1d Author: Arisu Tachibana <alicef <AT> gentoo <DOT> org> AuthorDate: Thu Aug 21 00:56:46 2025 +0000 Commit: Arisu Tachibana <alicef <AT> gentoo <DOT> org> CommitDate: Thu Aug 21 00:59:54 2025 +0000 URL: https://gitweb.gentoo.org/proj/linux-patches.git/commit/?id=26563a34
Revert "Add Update CPU Optimization patch for 6.16+" This reverts commit 110d64b0083ce8ab9ca1928905b4c27b21014981. "cc1: error: bad value (‘x86-64-v’) for ‘-march=’ switch" Signed-off-by: Arisu Tachibana <alicef <AT> gentoo.org> 0000_README | 4 - 5010_enable-cpu-optimizations-universal.patch | 846 -------------------------- 2 files changed, 850 deletions(-) diff --git a/0000_README b/0000_README index 8ee44525..77cb0499 100644 --- a/0000_README +++ b/0000_README @@ -95,10 +95,6 @@ Patch: 4567_distro-Gentoo-Kconfig.patch From: Tom Wijsman <[email protected]> Desc: Add Gentoo Linux support config settings and defaults. -Patch: 5010_enable-cpu-optimizations-universal.patch -From: https://github.com/graysky2/kernel_compiler_patch -Desc: More ISA levels and uarches for kernel 6.16+ - Patch: 5020_BMQ-and-PDS-io-scheduler-v6.16-r0.patch From: https://gitlab.com/alfredchen/projectc Desc: BMQ(BitMap Queue) Scheduler. A new CPU scheduler developed from PDS(incld). Inspired by the scheduler in zircon. diff --git a/5010_enable-cpu-optimizations-universal.patch b/5010_enable-cpu-optimizations-universal.patch deleted file mode 100644 index 962a82a6..00000000 --- a/5010_enable-cpu-optimizations-universal.patch +++ /dev/null @@ -1,846 +0,0 @@ -From 6b1d270f55e3143bcb3ad914adf920774351a6b9 Mon Sep 17 00:00:00 2001 -From: graysky <therealgraysky AT proton DOT me> -Date: Mon, 18 Aug 2025 04:14:48 -0400 - -1. New generic x86-64 ISA levels - -These are selectable under: - Processor type and features ---> x86-64 compiler ISA level - -• x86-64 A value of (1) is the default -• x86-64-v2 A value of (2) brings support for vector - instructions up to Streaming SIMD Extensions 4.2 (SSE4.2) - and Supplemental Streaming SIMD Extensions 3 (SSSE3), the - POPCNT instruction, and CMPXCHG16B. -• x86-64-v3 A value of (3) adds vector instructions up to AVX2, MOVBE, - and additional bit-manipulation instructions. - -There is also x86-64-v4 but including this makes little sense as -the kernel does not use any of the AVX512 instructions anyway. - -Users of glibc 2.33 and above can see which level is supported by running: - /lib/ld-linux-x86-64.so.2 --help | grep supported -Or - /lib64/ld-linux-x86-64.so.2 --help | grep supported - -2. New micro-architectures - -These are selectable under: - Processor type and features ---> Processor family - -• AMD Improved K8-family -• AMD K10-family -• AMD Family 10h (Barcelona) -• AMD Family 14h (Bobcat) -• AMD Family 16h (Jaguar) -• AMD Family 15h (Bulldozer) -• AMD Family 15h (Piledriver) -• AMD Family 15h (Steamroller) -• AMD Family 15h (Excavator) -• AMD Family 17h (Zen) -• AMD Family 17h (Zen 2) -• AMD Family 19h (Zen 3)** -• AMD Family 19h (Zen 4)‡ -• AMD Family 1Ah (Zen 5)§ -• Intel Silvermont low-power processors -• Intel Goldmont low-power processors (Apollo Lake and Denverton) -• Intel Goldmont Plus low-power processors (Gemini Lake) -• Intel 1st Gen Core i3/i5/i7 (Nehalem) -• Intel 1.5 Gen Core i3/i5/i7 (Westmere) -• Intel 2nd Gen Core i3/i5/i7 (Sandybridge) -• Intel 3rd Gen Core i3/i5/i7 (Ivybridge) -• Intel 4th Gen Core i3/i5/i7 (Haswell) -• Intel 5th Gen Core i3/i5/i7 (Broadwell) -• Intel 6th Gen Core i3/i5/i7 (Skylake) -• Intel 6th Gen Core i7/i9 (Skylake X) -• Intel 8th Gen Core i3/i5/i7 (Cannon Lake) -• Intel 10th Gen Core i7/i9 (Ice Lake) -• Intel Xeon (Cascade Lake) -• Intel Xeon (Cooper Lake)* -• Intel 3rd Gen 10nm++ i3/i5/i7/i9-family (Tiger Lake)* -• Intel 4th Gen 10nm++ Xeon (Sapphire Rapids)† -• Intel 11th Gen i3/i5/i7/i9-family (Rocket Lake)† -• Intel 12th Gen i3/i5/i7/i9-family (Alder Lake)† -• Intel 13th Gen i3/i5/i7/i9-family (Raptor Lake)‡ -• Intel 14th Gen i3/i5/i7/i9-family (Meteor Lake)‡ -• Intel 5th Gen 10nm++ Xeon (Emerald Rapids)‡ - -Notes: If not otherwise noted, gcc >=9.1 is required for support. - *Requires gcc >=10.1 or clang >=10.0 - **Required gcc >=10.3 or clang >=12.0 - †Required gcc >=11.1 or clang >=12.0 - ‡Required gcc >=13.0 or clang >=15.0.5 - §Required gcc >14.0 or clang >=19.0? - -3. Auto-detected micro-architecture levels - -Compile by passing the '-march=native' option which, "selects the CPU -to generate code for at compilation time by determining the processor type of -the compiling machine. Using -march=native enables all instruction subsets -supported by the local machine and will produce code optimized for the local -machine under the constraints of the selected instruction set."[1] - -Users of Intel CPUs should select the 'Intel-Native' option and users of AMD -CPUs should select the 'AMD-Native' option. - -MINOR NOTES RELATING TO INTEL ATOM PROCESSORS -This patch also changes -march=atom to -march=bonnell in accordance with the -gcc v4.9 changes. Upstream is using the deprecated -match=atom flags when I -believe it should use the newer -march=bonnell flag for atom processors.[2] - -It is not recommended to compile on Atom-CPUs with the 'native' option.[3] The -recommendation is to use the 'atom' option instead. - -BENEFITS -Small but real speed increases are measurable using a make endpoint comparing -a generic kernel to one built with one of the respective microarchs. - -See the following experimental evidence supporting this statement: -https://github.com/graysky2/kernel_compiler_patch?tab=readme-ov-file#benchmarks - -REQUIREMENTS -linux version 6.16+ -gcc version >=9.0 or clang version >=9.0 - -ACKNOWLEDGMENTS -This patch builds on the seminal work by Jeroen.[4] - -REFERENCES -1. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html#index-x86-Options -2. https://bugzilla.kernel.org/show_bug.cgi?id=77461 -3. https://github.com/graysky2/kernel_gcc_patch/issues/15 -4. http://www.linuxforge.net/docs/linux/linux-gcc.php - ---- - arch/x86/Kconfig.cpu | 427 ++++++++++++++++++++++++++++++++++++++++++- - arch/x86/Makefile | 213 ++++++++++++++++++++- - 2 files changed, 631 insertions(+), 9 deletions(-) - -diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu -index f928cf6e3252..2802936f2e62 100644 ---- a/arch/x86/Kconfig.cpu -+++ b/arch/x86/Kconfig.cpu -@@ -31,6 +31,7 @@ choice - - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. - - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). - - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). -+ - "Opteron/Athlon64/Hammer/K8" for all K8 and newer AMD CPUs. - - "Crusoe" for the Transmeta Crusoe series. - - "Efficeon" for the Transmeta Efficeon series. - - "Winchip-C6" for original IDT Winchip. -@@ -41,7 +42,10 @@ choice - - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. - - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). - - "VIA C7" for VIA C7. -+ - "Intel P4" for the Pentium 4/Netburst microarchitecture. -+ - "Core 2/newer Xeon" for all core2 and newer Intel CPUs. - - "Intel Atom" for the Atom-microarchitecture CPUs. -+ - "Generic-x86-64" for a kernel which runs on any x86-64 CPU. - - See each option's help text for additional details. If you don't know - what to do, choose "Pentium-Pro". -@@ -135,10 +139,21 @@ config MPENTIUM4 - -Mobile Pentium 4 - -Mobile Pentium 4 M - -Extreme Edition (Gallatin) -+ -Prescott -+ -Prescott 2M -+ -Cedar Mill -+ -Presler -+ -Smithfiled - Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename: - -Foster - -Prestonia - -Gallatin -+ -Nocona -+ -Irwindale -+ -Cranford -+ -Potomac -+ -Paxville -+ -Dempsey - - config MK6 - bool "K6/K6-II/K6-III" -@@ -281,6 +296,402 @@ config X86_GENERIC - This is really intended for distributors who need more - generic optimizations. - -+choice -+ prompt "x86_64 Compiler Build Optimization" -+ depends on !X86_NATIVE_CPU -+ default GENERIC_CPU -+ -+config GENERIC_CPU -+ bool "Generic-x86-64" -+ depends on X86_64 -+ help -+ Generic x86-64 CPU. -+ Runs equally well on all x86-64 CPUs. -+ -+config MK8 -+ bool "AMD Opteron/Athlon64/Hammer/K8" -+ help -+ Select this for an AMD Opteron or Athlon64 Hammer-family processor. -+ Enables use of some extended instructions, and passes appropriate -+ optimization flags to GCC. -+ -+config MK8SSE3 -+ bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3" -+ help -+ Select this for improved AMD Opteron or Athlon64 Hammer-family processors. -+ Enables use of some extended instructions, and passes appropriate -+ optimization flags to GCC. -+ -+config MK10 -+ bool "AMD 61xx/7x50/PhenomX3/X4/II/K10" -+ help -+ Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50, -+ Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor. -+ Enables use of some extended instructions, and passes appropriate -+ optimization flags to GCC. -+ -+config MBARCELONA -+ bool "AMD Barcelona" -+ help -+ Select this for AMD Family 10h Barcelona processors. -+ -+ Enables -march=barcelona -+ -+config MBOBCAT -+ bool "AMD Bobcat" -+ help -+ Select this for AMD Family 14h Bobcat processors. -+ -+ Enables -march=btver1 -+ -+config MJAGUAR -+ bool "AMD Jaguar" -+ help -+ Select this for AMD Family 16h Jaguar processors. -+ -+ Enables -march=btver2 -+ -+config MBULLDOZER -+ bool "AMD Bulldozer" -+ help -+ Select this for AMD Family 15h Bulldozer processors. -+ -+ Enables -march=bdver1 -+ -+config MPILEDRIVER -+ bool "AMD Piledriver" -+ help -+ Select this for AMD Family 15h Piledriver processors. -+ -+ Enables -march=bdver2 -+ -+config MSTEAMROLLER -+ bool "AMD Steamroller" -+ help -+ Select this for AMD Family 15h Steamroller processors. -+ -+ Enables -march=bdver3 -+ -+config MEXCAVATOR -+ bool "AMD Excavator" -+ help -+ Select this for AMD Family 15h Excavator processors. -+ -+ Enables -march=bdver4 -+ -+config MZEN -+ bool "AMD Ryzen" -+ help -+ Select this for AMD Family 17h Zen processors. -+ -+ Enables -march=znver1 -+ -+config MZEN2 -+ bool "AMD Ryzen 2" -+ help -+ Select this for AMD Family 17h Zen 2 processors. -+ -+ Enables -march=znver2 -+ -+config MZEN3 -+ bool "AMD Ryzen 3" -+ depends on (CC_IS_GCC && GCC_VERSION >= 100300) || (CC_IS_CLANG && CLANG_VERSION >= 120000) -+ help -+ Select this for AMD Family 19h Zen 3 processors. -+ -+ Enables -march=znver3 -+ -+config MZEN4 -+ bool "AMD Ryzen 4" -+ depends on (CC_IS_GCC && GCC_VERSION >= 130000) || (CC_IS_CLANG && CLANG_VERSION >= 160000) -+ help -+ Select this for AMD Family 19h Zen 4 processors. -+ -+ Enables -march=znver4 -+ -+config MZEN5 -+ bool "AMD Ryzen 5" -+ depends on (CC_IS_GCC && GCC_VERSION > 140000) || (CC_IS_CLANG && CLANG_VERSION >= 190100) -+ help -+ Select this for AMD Family 19h Zen 5 processors. -+ -+ Enables -march=znver5 -+ -+config MPSC -+ bool "Intel P4 / older Netburst based Xeon" -+ depends on X86_64 -+ help -+ Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey -+ Xeon CPUs with Intel 64bit which is compatible with x86-64. -+ Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the -+ Netburst core and shouldn't use this option. You can distinguish them -+ using the cpu family field -+ in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. -+ -+config MCORE2 -+ bool "Intel Core 2" -+ depends on X86_64 -+ help -+ -+ Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and -+ 53xx) CPUs. You can distinguish newer from older Xeons by the CPU -+ family in /proc/cpuinfo. Newer ones have 6 and older ones 15 -+ (not a typo) -+ -+ Enables -march=core2 -+ -+config MNEHALEM -+ bool "Intel Nehalem" -+ depends on X86_64 -+ help -+ -+ Select this for 1st Gen Core processors in the Nehalem family. -+ -+ Enables -march=nehalem -+ -+config MWESTMERE -+ bool "Intel Westmere" -+ depends on X86_64 -+ help -+ -+ Select this for the Intel Westmere formerly Nehalem-C family. -+ -+ Enables -march=westmere -+ -+config MSILVERMONT -+ bool "Intel Silvermont" -+ depends on X86_64 -+ help -+ -+ Select this for the Intel Silvermont platform. -+ -+ Enables -march=silvermont -+ -+config MGOLDMONT -+ bool "Intel Goldmont" -+ depends on X86_64 -+ help -+ -+ Select this for the Intel Goldmont platform including Apollo Lake and Denverton. -+ -+ Enables -march=goldmont -+ -+config MGOLDMONTPLUS -+ bool "Intel Goldmont Plus" -+ depends on X86_64 -+ help -+ -+ Select this for the Intel Goldmont Plus platform including Gemini Lake. -+ -+ Enables -march=goldmont-plus -+ -+config MSANDYBRIDGE -+ bool "Intel Sandy Bridge" -+ depends on X86_64 -+ help -+ -+ Select this for 2nd Gen Core processors in the Sandy Bridge family. -+ -+ Enables -march=sandybridge -+ -+config MIVYBRIDGE -+ bool "Intel Ivy Bridge" -+ depends on X86_64 -+ help -+ -+ Select this for 3rd Gen Core processors in the Ivy Bridge family. -+ -+ Enables -march=ivybridge -+ -+config MHASWELL -+ bool "Intel Haswell" -+ depends on X86_64 -+ help -+ -+ Select this for 4th Gen Core processors in the Haswell family. -+ -+ Enables -march=haswell -+ -+config MBROADWELL -+ bool "Intel Broadwell" -+ depends on X86_64 -+ help -+ -+ Select this for 5th Gen Core processors in the Broadwell family. -+ -+ Enables -march=broadwell -+ -+config MSKYLAKE -+ bool "Intel Skylake" -+ depends on X86_64 -+ help -+ -+ Select this for 6th Gen Core processors in the Skylake family. -+ -+ Enables -march=skylake -+ -+config MSKYLAKEX -+ bool "Intel Skylake-X (7th Gen Core i7/i9)" -+ depends on X86_64 -+ help -+ -+ Select this for 7th Gen Core i7/i9 processors in the Skylake-X family. -+ -+ Enables -march=skylake-avx512 -+ -+config MCANNONLAKE -+ bool "Intel Coffee Lake/Kaby Lake Refresh (8th Gen Core i3/i5/i7)" -+ depends on X86_64 -+ help -+ -+ Select this for 8th Gen Core i3/i5/i7 processors in the Coffee Lake or Kaby Lake Refresh families. -+ -+ Enables -march=cannonlake -+ -+config MICELAKE_CLIENT -+ bool "Intel Ice Lake" -+ depends on X86_64 -+ help -+ -+ Select this for 10th Gen Core client processors in the Ice Lake family. -+ -+ Enables -march=icelake-client -+ -+config MICELAKE_SERVER -+ bool "Intel Ice Lake-SP (3rd Gen Xeon Scalable)" -+ depends on X86_64 -+ help -+ -+ Select this for 3rd Gen Xeon Scalable processors in the Ice Lake-SP family. -+ -+ Enables -march=icelake-server -+ -+config MCOOPERLAKE -+ bool "Intel Cooper Lake" -+ depends on X86_64 -+ depends on (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000) -+ help -+ -+ Select this for Xeon processors in the Cooper Lake family. -+ -+ Enables -march=cooperlake -+ -+config MCASCADELAKE -+ bool "Intel Cascade Lake" -+ depends on X86_64 -+ depends on (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000) -+ help -+ -+ Select this for Xeon processors in the Cascade Lake family. -+ -+ Enables -march=cascadelake -+ -+config MTIGERLAKE -+ bool "Intel Tiger Lake" -+ depends on X86_64 -+ depends on (CC_IS_GCC && GCC_VERSION > 100100) || (CC_IS_CLANG && CLANG_VERSION >= 100000) -+ help -+ -+ Select this for third-generation 10 nm process processors in the Tiger Lake family. -+ -+ Enables -march=tigerlake -+ -+config MSAPPHIRERAPIDS -+ bool "Intel Sapphire Rapids" -+ depends on X86_64 -+ depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000) -+ help -+ -+ Select this for fourth-generation 10 nm process processors in the Sapphire Rapids family. -+ -+ Enables -march=sapphirerapids -+ -+config MROCKETLAKE -+ bool "Intel Rocket Lake" -+ depends on X86_64 -+ depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000) -+ help -+ -+ Select this for eleventh-generation processors in the Rocket Lake family. -+ -+ Enables -march=rocketlake -+ -+config MALDERLAKE -+ bool "Intel Alder Lake" -+ depends on X86_64 -+ depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000) -+ help -+ -+ Select this for twelfth-generation processors in the Alder Lake family. -+ -+ Enables -march=alderlake -+ -+config MRAPTORLAKE -+ bool "Intel Raptor Lake" -+ depends on X86_64 -+ depends on (CC_IS_GCC && GCC_VERSION >= 130000) || (CC_IS_CLANG && CLANG_VERSION >= 150500) -+ help -+ -+ Select this for thirteenth-generation processors in the Raptor Lake family. -+ -+ Enables -march=raptorlake -+ -+config MMETEORLAKE -+ bool "Intel Meteor Lake" -+ depends on X86_64 -+ depends on (CC_IS_GCC && GCC_VERSION >= 130000) || (CC_IS_CLANG && CLANG_VERSION >= 150500) -+ help -+ -+ Select this for fourteenth-generation processors in the Meteor Lake family. -+ -+ Enables -march=meteorlake -+ -+config MEMERALDRAPIDS -+ bool "Intel Emerald Rapids" -+ depends on X86_64 -+ depends on (CC_IS_GCC && GCC_VERSION > 130000) || (CC_IS_CLANG && CLANG_VERSION >= 150500) -+ help -+ -+ Select this for fifth-generation Xeon Scalable processors in the Emerald Rapids family. -+ -+ Enables -march=emeraldrapids -+ -+config MDIAMONDRAPIDS -+ bool "Intel Diamond Rapids (7th Gen Xeon Scalable)" -+ depends on X86_64 -+ depends on (CC_IS_GCC && GCC_VERSION > 150000) || (CC_IS_CLANG && CLANG_VERSION >= 200000) -+ help -+ -+ Select this for seventh-generation Xeon Scalable processors in the Diamond Rapids family. -+ -+ Enables -march=diamondrapids -+ -+endchoice -+ -+config X86_64_VERSION -+ int "x86-64 compiler ISA level" -+ range 1 3 -+ depends on (CC_IS_GCC && GCC_VERSION > 110000) || (CC_IS_CLANG && CLANG_VERSION >= 120000) -+ depends on X86_64 && GENERIC_CPU -+ help -+ Specify a specific x86-64 compiler ISA level. -+ -+ There are three x86-64 ISA levels that work on top of -+ the x86-64 baseline, namely: x86-64-v2 and x86-64-v3. -+ -+ x86-64-v2 brings support for vector instructions up to Streaming SIMD -+ Extensions 4.2 (SSE4.2) and Supplemental Streaming SIMD Extensions 3 -+ (SSSE3), the POPCNT instruction, and CMPXCHG16B. -+ -+ x86-64-v3 adds vector instructions up to AVX2, MOVBE, and additional -+ bit-manipulation instructions. -+ -+ x86-64-v4 is not included since the kernel does not use AVX512 instructions -+ -+ You can find the best version for your CPU by running one of the following: -+ /lib/ld-linux-x86-64.so.2 --help | grep supported -+ /lib64/ld-linux-x86-64.so.2 --help | grep supported -+ - # - # Define implied options from the CPU selection here - config X86_INTERNODE_CACHE_SHIFT -@@ -290,8 +701,8 @@ config X86_INTERNODE_CACHE_SHIFT - - config X86_L1_CACHE_SHIFT - int -- default "7" if MPENTIUM4 -- default "6" if MK7 || MPENTIUMM || MATOM || MVIAC7 || X86_GENERIC || X86_64 -+ default "7" if MPENTIUM4 || MPSC -+ default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MZEN4 || MZEN5 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE_CLIENT || MICELAKE_SERVER || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MDIAMONDRAPIDS || X86_NATIVE_CPU - default "4" if MELAN || M486SX || M486 || MGEODEGX1 - default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX - -@@ -309,19 +720,19 @@ config X86_ALIGNMENT_16 - - config X86_INTEL_USERCOPY - def_bool y -- depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK7 || MEFFICEON -+ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE_CLIENT || MICELAKE_SERVER || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MDIAMONDRAPIDS - - config X86_USE_PPRO_CHECKSUM - def_bool y -- depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MATOM -+ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MJAGUAR || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MZEN2 || MZEN3 || MZEN4 || MZEN5 || MNEHALEM || MWESTMERE || MSILVERMONT || MGOLDMONT || MGOLDMONTPLUS || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE_CLIENT || MICELAKE_SERVER || MCASCADELAKE || MCOOPERLAKE || MTIGERLAKE || MSAPPHIRERAPIDS || MROCKETLAKE || MALDERLAKE || MRAPTORLAKE || MMETEORLAKE || MEMERALDRAPIDS || MDIAMONDRAPIDS - - config X86_TSC - def_bool y -- depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MATOM) || X86_64 -+ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64 - - config X86_HAVE_PAE - def_bool y -- depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64 -+ depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC7 || MCORE2 || MATOM || X86_64 - - config X86_CX8 - def_bool y -@@ -331,12 +742,12 @@ config X86_CX8 - # generates cmov. - config X86_CMOV - def_bool y -- depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || MATOM || MGEODE_LX || X86_64) -+ depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX) - - config X86_MINIMUM_CPU_FAMILY - int - default "64" if X86_64 -- default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MK7) -+ default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCORE2 || MK7 || MK8) - default "5" if X86_32 && X86_CX8 - default "4" - -diff --git a/arch/x86/Makefile b/arch/x86/Makefile -index 1913d342969b..6c165daccb3d 100644 ---- a/arch/x86/Makefile -+++ b/arch/x86/Makefile -@@ -177,10 +177,221 @@ ifdef CONFIG_X86_NATIVE_CPU - KBUILD_CFLAGS += -march=native - KBUILD_RUSTFLAGS += -Ctarget-cpu=native - else -+ifdef CONFIG_MK8 -+ KBUILD_CFLAGS += -march=k8 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=k8 -+endif -+ -+ifdef CONFIG_MK8SSE3 -+ KBUILD_CFLAGS += -march=k8-sse3 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=k8-sse3 -+endif -+ -+ifdef CONFIG_MK10 -+ KBUILD_CFLAGS += -march=amdfam10 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=amdfam10 -+endif -+ -+ifdef CONFIG_MBARCELONA -+ KBUILD_CFLAGS += -march=barcelona -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=barcelona -+endif -+ -+ifdef CONFIG_MBOBCAT -+ KBUILD_CFLAGS += -march=btver1 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=btver1 -+endif -+ -+ifdef CONFIG_MJAGUAR -+ KBUILD_CFLAGS += -march=btver2 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=btver2 -+endif -+ -+ifdef CONFIG_MBULLDOZER -+ KBUILD_CFLAGS += -march=bdver1 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=bdver1 -+endif -+ -+ifdef CONFIG_MPILEDRIVER -+ KBUILD_CFLAGS += -march=bdver2 -mno-tbm -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=bdver2 -mno-tbm -+endif -+ -+ifdef CONFIG_MSTEAMROLLER -+ KBUILD_CFLAGS += -march=bdver3 -mno-tbm -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=bdver3 -mno-tbm -+endif -+ -+ifdef CONFIG_MEXCAVATOR -+ KBUILD_CFLAGS += -march=bdver4 -mno-tbm -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=bdver4 -mno-tbm -+endif -+ -+ifdef CONFIG_MZEN -+ KBUILD_CFLAGS += -march=znver1 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=znver1 -+endif -+ -+ifdef CONFIG_MZEN2 -+ KBUILD_CFLAGS += -march=znver2 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=znver2 -+endif -+ -+ifdef CONFIG_MZEN3 -+ KBUILD_CFLAGS += -march=znver3 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=znver3 -+endif -+ -+ifdef CONFIG_MZEN4 -+ KBUILD_CFLAGS += -march=znver4 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=znver4 -+endif -+ -+ifdef CONFIG_MZEN5 -+ KBUILD_CFLAGS += -march=znver5 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=znver5 -+endif -+ -+ifdef CONFIG_MPSC -+ KBUILD_CFLAGS += -march=nocona -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=nocona -+endif -+ -+ifdef CONFIG_MCORE2 -+ KBUILD_CFLAGS += -march=core2 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=core2 -+endif -+ -+ifdef CONFIG_MNEHALEM -+ KBUILD_CFLAGS += -march=nehalem -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=nehalem -+endif -+ -+ifdef CONFIG_MWESTMERE -+ KBUILD_CFLAGS += -march=westmere -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=westmere -+endif -+ -+ifdef CONFIG_MSILVERMONT -+ KBUILD_CFLAGS += -march=silvermont -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=silvermont -+endif -+ -+ifdef CONFIG_MGOLDMONT -+ KBUILD_CFLAGS += -march=goldmont -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=goldmont -+endif -+ -+ifdef CONFIG_MGOLDMONTPLUS -+ KBUILD_CFLAGS += -march=goldmont-plus -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=goldmont-plus -+endif -+ -+ifdef CONFIG_MSANDYBRIDGE -+ KBUILD_CFLAGS += -march=sandybridge -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=sandybridge -+endif -+ -+ifdef CONFIG_MIVYBRIDGE -+ KBUILD_CFLAGS += -march=ivybridge -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=ivybridge -+endif -+ -+ifdef CONFIG_MHASWELL -+ KBUILD_CFLAGS += -march=haswell -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=haswell -+endif -+ -+ifdef CONFIG_MBROADWELL -+ KBUILD_CFLAGS += -march=broadwell -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=broadwell -+endif -+ -+ifdef CONFIG_MSKYLAKE -+ KBUILD_CFLAGS += -march=skylake -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=skylake -+endif -+ -+ifdef CONFIG_MSKYLAKEX -+ KBUILD_CFLAGS += -march=skylake-avx512 -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=skylake-avx512 -+endif -+ -+ifdef CONFIG_MCANNONLAKE -+ KBUILD_CFLAGS += -march=cannonlake -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=cannonlake -+endif -+ -+ifdef CONFIG_MICELAKE_CLIENT -+ KBUILD_CFLAGS += -march=icelake-client -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=icelake-client -+endif -+ -+ifdef CONFIG_MICELAKE_SERVER -+ KBUILD_CFLAGS += -march=icelake-server -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=icelake-server -+endif -+ -+ifdef CONFIG_MCOOPERLAKE -+ KBUILD_CFLAGS += -march=cooperlake -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=cooperlake -+endif -+ -+ifdef CONFIG_MCASCADELAKE -+ KBUILD_CFLAGS += -march=cascadelake -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=cascadelake -+endif -+ -+ifdef CONFIG_MTIGERLAKE -+ KBUILD_CFLAGS += -march=tigerlake -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=tigerlake -+endif -+ -+ifdef CONFIG_MSAPPHIRERAPIDS -+ KBUILD_CFLAGS += -march=sapphirerapids -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=sapphirerapids -+endif -+ -+ifdef CONFIG_MROCKETLAKE -+ KBUILD_CFLAGS += -march=rocketlake -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=rocketlake -+endif -+ -+ifdef CONFIG_MALDERLAKE -+ KBUILD_CFLAGS += -march=alderlake -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=alderlake -+endif -+ -+ifdef CONFIG_MRAPTORLAKE -+ KBUILD_CFLAGS += -march=raptorlake -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=raptorlake -+endif -+ -+ifdef CONFIG_MMETEORLAKE -+ KBUILD_CFLAGS += -march=meteorlake -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=meteorlake -+endif -+ -+ifdef CONFIG_MEMERALDRAPIDS -+ KBUILD_CFLAGS += -march=emeraldrapids -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=emeraldrapids -+endif -+ -+ifdef CONFIG_MDIAMONDRAPIDS -+ KBUILD_CFLAGS += -march=diamondrapids -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=diamondrapids -+endif -+ -+ifdef CONFIG_GENERIC_CPU -+ifeq ($(CONFIG_X86_64_VERSION),1) - KBUILD_CFLAGS += -march=x86-64 -mtune=generic - KBUILD_RUSTFLAGS += -Ctarget-cpu=x86-64 -Ztune-cpu=generic -+else -+ KBUILD_CFLAGS +=-march=x86-64-v$(CONFIG_X86_64_VERSION) -+ KBUILD_RUSTFLAGS += -Ctarget-cpu=x86-64-v$(CONFIG_X86_64_VERSION) -+endif -+endif - endif -- - KBUILD_CFLAGS += -mno-red-zone - KBUILD_CFLAGS += -mcmodel=kernel - KBUILD_RUSTFLAGS += -Cno-redzone=y --- -2.50.1 -
