Hi The following interrupt control definition doesn't seem to work for RISCV builds, while it does for X86. system.cpu.createInterruptController()system.cpu.interrupts[0].pio = system.membus.mem_side_portssystem.cpu.interrupts[0].int_requestor = system.membus.cpu_side_portssystem.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
Wondering if there is any name/type change. Could you point me to relevant documents. regardsRobert K
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