" system.cohere = MESI_Two_Level()"
That line is your problem. When you "import *" from m5.objects it imports
the *module* MESI_Two_Level, not the object. You probably need to use this
instead:
https://github.com/gem5/gem5/blob/stable/src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py#L53
Cheers,
Jason
On Thu, Feb 20, 2025 at 11:53 AM Beser, Nicholas D. via gem5-users <
gem5-users@gem5.org> wrote:
> I am trying to create a O3CPU based design with a 3 level cache (4 cores).
> I am running into an error with O3CPU, and I am not sure if what I am
> trying todo is possible with gem5.
>
>
>
> Here is the code:
>
> from m5.objects import *
>
> from m5 import instantiate, simulate, curTick
>
>
>
> # Create the system
>
> system = System()
>
> system.clk_domain = SrcClockDomain(clock="2GHz",
> voltage_domain=VoltageDomain())
>
> system.mem_mode = 'timing' # Required for cache simulation
>
> system.mem_ranges = [AddrRange("512MB")]
>
>
>
> # CPU configuration (4-core system)
>
> system.cpu = [O3CPU() for i in range(4)] # Out-of-order execution model
>
>
>
> # L1 Caches (Private to each core)
>
> for cpu in system.cpu:
>
> cpu.icache = Cache(size="32kB", assoc=8, tag_latency=2,
> data_latency=2, response_latency=2,
>
> mshrs=4, tgts_per_mshr=20)
>
> cpu.dcache = Cache(size="32kB", assoc=8, tag_latency=2,
> data_latency=2, response_latency=2,
>
> mshrs=4, tgts_per_mshr=20)
>
>
>
> cpu.icache_port = cpu.icache.cpu_side
>
> cpu.dcache_port = cpu.dcache.cpu_side
>
>
>
> # L2 Cache (Shared by two cores each)
>
> system.l2bus = L2XBar()
>
> system.l2cache = [Cache(size="512kB", assoc=8, tag_latency=10,
> data_latency=10, response_latency=10,
>
> mshrs=20, tgts_per_mshr=12) for _ in range(2)]
>
>
>
> # Connect L1 caches to L2 caches (2 CPUs per L2)
>
> for i in range(4):
>
> system.cpu[i].icache.mem_side = system.l2bus.slave
>
> system.cpu[i].dcache.mem_side = system.l2bus.slave
>
> if i < 2:
>
> system.l2cache[0].cpu_side = system.l2bus.master
>
> else:
>
> system.l2cache[1].cpu_side = system.l2bus.master
>
>
>
> # L3 Cache (Shared across all cores)
>
> system.l3bus = L2XBar()
>
> system.l3cache = Cache(size="4MB", assoc=16, tag_latency=20,
> data_latency=20, response_latency=20,
>
> mshrs=20, tgts_per_mshr=12)
>
> system.l2cache[0].mem_side = system.l3bus.slave
>
> system.l2cache[1].mem_side = system.l3bus.slave
>
> system.l3cache.cpu_side = system.l3bus.master
>
>
>
> # Connecting L3 to memory bus
>
> system.membus = SystemXBar()
>
> system.l3cache.mem_side = system.membus.slave
>
>
>
> # Memory controller
>
> system.mem_ctrl = DDR3_1600_8x8(range=system.mem_ranges[0])
>
> system.mem_ctrl.port = system.membus.master
>
>
>
> # Enable MESI coherence protocol
>
> system.cohere = MESI_Two_Level()
>
> system.timingSimpleCPU = system.cpu # Ensures MESI is applied to CPUs
>
>
>
> # Interrupt Controller for each CPU
>
> for cpu in system.cpu:
>
> cpu.createInterruptController()
>
>
>
> # System port
>
> system.system_port = system.membus.slave
>
>
>
> # Binary to Execute (x86 Binary)
>
> binary = "piTimeX86"
>
> system.workload = SEWorkload.init_compatible(binary)
>
>
>
> # Assign workload to all CPUs
>
> for cpu in system.cpu:
>
> cpu.workload = system.workload
>
> cpu.createThreads()
>
>
>
> # Root object
>
> root = Root(full_system=False, system=system)
>
> instantiate()
>
>
>
> print("Starting simulation...")
>
> exit_event = simulate()
>
> print("Exiting @ tick {} because {}".format(curTick(),
> exit_event.getCause()))
>
>
>
> When I attempt to run this, I am getting the following error:
>
>
>
> $ ge
>
> m5.opt fourcore3levelcache.py
>
> gem5 Simulator System. https://www.gem5.org
>
> gem5 is copyrighted software; use the --copyright option for details.
>
>
>
> gem5 version 24.0.0.0
>
> gem5 compiled Jan 11 2025 10:30:05
>
> gem5 started Feb 20 2025 14:36:06
>
> gem5 executing on ubuntu, pid 268187
>
> command line: gem5.opt fourcore3levelcache.py
>
>
>
> TypeError: 'module' object is not callable
>
>
>
> At:
>
> fourcore3levelcache.py(11): <listcomp>
>
> fourcore3levelcache.py(11): <module>
>
> src/python/m5/main.py(669): main
>
>
>
> The error is on the O3CPU line. I can use some advise if there is a way of
> running a 3 level cache with a binary executable. I would prefer to use
> O3CPU since I want my class to experiment with the different O3CPU
> resources.
>
>
>
> Nick
>
>
>
>
> _______________________________________________
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>
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