Hi, I am working on modifying the MESI_Two_Level_L1cache.sm state machine file to enable inter-core cache sharing. Specifically, my goal is that during a CPU Load or Ifetch request, when there's a miss in the L1 cache of core-1, the request should be forwarded to the neighboring core (core-2).
I am running the same workload (SPEC CPU2006-lbm) on both cores, and I believe that, at runtime, both cores should require the same cache blocks, as the workload is identical. However, despite modifying the state machine file to support this configuration, I am not observing any hits from the neighboring core. As I am relatively new to this, I would appreciate some guidance in resolving this issue. I have attached the modified MESI_Two_Level_L1cache.sm state machine SLICC file for your reference. Thank you for your help! Best regards, Jagadeesh
MESI_Two_Level-L1cache.sm
Description: application/vnd.stepmania.stepchart
_______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
